#define一覧 C#

VisualCsharp2010

No. 名称 ファイル名 説明
1
ERRFILEERRFILE ERRFILE_ath5k ath5k.h  
2
PCI_DEVICE_ID_ATHEROS_AR5210PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 ath5k.h AR5210
3
PCI_DEVICE_ID_ATHEROS_AR5311PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 ath5k.h AR5311
4
PCI_DEVICE_ID_ATHEROS_AR5211PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 ath5k.h AR5211
5
PCI_DEVICE_ID_ATHEROS_AR5212PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 ath5k.h AR5212
6
PCI_DEVICE_ID_3COM_3CRDAG675PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 ath5k.h 3CRDAG675 (Atheros AR5212)
7
PCI_DEVICE_ID_3COM_2_3CRPAG175PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 ath5k.h 3CRPAG175 (Atheros AR5212)
8
PCI_DEVICE_ID_ATHEROS_AR5210_APPCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 ath5k.h AR5210 (Early)
9
PCI_DEVICE_ID_ATHEROS_AR5212_IBPCI_DEVICE_ID_ATHEROS_AR5212_IB 0x1014 ath5k.h AR5212 (IBM MiniPCI)
10
PCI_DEVICE_ID_ATHEROS_AR5210_DEPCI_DEVICE_ID_ATHEROS_AR5210_DE 0x1107 ath5k.h AR5210 (no eeprom)
11
PCI_DEVICE_ID_ATHEROS_AR5212_DEPCI_DEVICE_ID_ATHEROS_AR5212_DE 0x1113 ath5k.h AR5212 (no eeprom)
12
PCI_DEVICE_ID_ATHEROS_AR5211_DEPCI_DEVICE_ID_ATHEROS_AR5211_DE 0x1112 ath5k.h AR5211 (no eeprom)
13
PCI_DEVICE_ID_ATHEROS_AR5212_FPPCI_DEVICE_ID_ATHEROS_AR5212_FP 0xf013 ath5k.h AR5212 (emulation board)
14
PCI_DEVICE_ID_ATHEROS_AR5211_LEPCI_DEVICE_ID_ATHEROS_AR5211_LE 0xff12 ath5k.h AR5211 (emulation board)
15
PCI_DEVICE_ID_ATHEROS_AR5211_FPPCI_DEVICE_ID_ATHEROS_AR5211_FP 0xf11b ath5k.h AR5211 (emulation board)
16
PCI_DEVICE_ID_ATHEROS_AR5312_REPCI_DEVICE_ID_ATHEROS_AR5312_RE 0x0052 ath5k.h AR5312 WMAC (AP31)
17
PCI_DEVICE_ID_ATHEROS_AR5312_REPCI_DEVICE_ID_ATHEROS_AR5312_RE 0x0057 ath5k.h AR5312 WMAC (AP30-040)
18
PCI_DEVICE_ID_ATHEROS_AR5312_REPCI_DEVICE_ID_ATHEROS_AR5312_RE 0x0058 ath5k.h AR5312 WMAC (AP43-030)
19
PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0014 ath5k.h AR5212 compatible
20
PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0015 ath5k.h AR5212 compatible
21
PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0016 ath5k.h AR5212 compatible
22
PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0017 ath5k.h AR5212 compatible
23
PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0018 ath5k.h AR5212 compatible
24
PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0019 ath5k.h AR5212 compatible
25
PCI_DEVICE_ID_ATHEROS_AR2413PCI_DEVICE_ID_ATHEROS_AR2413 0x001a ath5k.h AR2413 (Griffin-lite)
26
PCI_DEVICE_ID_ATHEROS_AR5413PCI_DEVICE_ID_ATHEROS_AR5413 0x001b ath5k.h AR5413 (Eagle)
27
PCI_DEVICE_ID_ATHEROS_AR5424PCI_DEVICE_ID_ATHEROS_AR5424 0x001c ath5k.h AR5424 (Condor PCI-E)
28
PCI_DEVICE_ID_ATHEROS_AR5416PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 ath5k.h AR5416
29
PCI_DEVICE_ID_ATHEROS_AR5418PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 ath5k.h AR5418
30
AR5K_INI_RFGAIN_5GHZAR5K_INI_RFGAIN_5GHZ 0 ath5k.h  
31
AR5K_INI_RFGAIN_2GHZAR5K_INI_RFGAIN_2GHZ 1 ath5k.h  
32
AR5K_INI_VAL_11AAR5K_INI_VAL_11A 0 ath5k.h  
33
AR5K_INI_VAL_11A_TURBOAR5K_INI_VAL_11A_TURBO 1 ath5k.h  
34
AR5K_INI_VAL_11BAR5K_INI_VAL_11B 2 ath5k.h  
35
AR5K_INI_VAL_11GAR5K_INI_VAL_11G 3 ath5k.h  
36
AR5K_INI_VAL_11G_TURBOAR5K_INI_VAL_11G_TURBO 4 ath5k.h  
37
AR5K_INI_VAL_XRAR5K_INI_VAL_XR 0 ath5k.h  
38
AR5K_INI_VAL_MAXAR5K_INI_VAL_MAX 5 ath5k.h  
39
IEEE80211_MAX_LENIEEE80211_MAX_LEN 2352 ath5k.h  
40
AR5K_TUNE_DMA_BEACON_RESPAR5K_TUNE_DMA_BEACON_RESP 2 ath5k.h  
41
AR5K_TUNE_SW_BEACON_RESPAR5K_TUNE_SW_BEACON_RESP 10 ath5k.h  
42
AR5K_TUNE_ADDITIONAL_SWBA_BACKOAR5K_TUNE_ADDITIONAL_SWBA_BACKO 0 ath5k.h  
43
AR5K_TUNE_RADAR_ALERTAR5K_TUNE_RADAR_ALERT 0 ath5k.h  
44
AR5K_TUNE_MIN_TX_FIFO_THRESAR5K_TUNE_MIN_TX_FIFO_THRES 1 ath5k.h  
45
AR5K_TUNE_MAX_TX_FIFO_THRESAR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) ath5k.h  
46
AR5K_TUNE_REGISTER_TIMEOUTAR5K_TUNE_REGISTER_TIMEOUT 20000 ath5k.h  
47
AR5K_TUNE_RSSI_THRESAR5K_TUNE_RSSI_THRES 129 ath5k.h  
48
AR5K_TUNE_BMISS_THRESAR5K_TUNE_BMISS_THRES 7 ath5k.h  
49
AR5K_TUNE_REGISTER_DWELL_TIMEAR5K_TUNE_REGISTER_DWELL_TIME 20000 ath5k.h  
50
AR5K_TUNE_BEACON_INTERVALAR5K_TUNE_BEACON_INTERVAL 100 ath5k.h  
51
AR5K_TUNE_AIFSAR5K_TUNE_AIFS 2 ath5k.h  
52
AR5K_TUNE_AIFS_11BAR5K_TUNE_AIFS_11B 2 ath5k.h  
53
AR5K_TUNE_AIFS_XRAR5K_TUNE_AIFS_XR 0 ath5k.h  
54
AR5K_TUNE_CWMINAR5K_TUNE_CWMIN 15 ath5k.h  
55
AR5K_TUNE_CWMIN_11BAR5K_TUNE_CWMIN_11B 31 ath5k.h  
56
AR5K_TUNE_CWMIN_XRAR5K_TUNE_CWMIN_XR 3 ath5k.h  
57
AR5K_TUNE_CWMAXAR5K_TUNE_CWMAX 1023 ath5k.h  
58
AR5K_TUNE_CWMAX_11BAR5K_TUNE_CWMAX_11B 1023 ath5k.h  
59
AR5K_TUNE_CWMAX_XRAR5K_TUNE_CWMAX_XR 7 ath5k.h  
60
AR5K_TUNE_NOISE_FLOORAR5K_TUNE_NOISE_FLOOR -72 ath5k.h  
61
AR5K_TUNE_MAX_TXPOWERAR5K_TUNE_MAX_TXPOWER 63 ath5k.h  
62
AR5K_TUNE_DEFAULT_TXPOWERAR5K_TUNE_DEFAULT_TXPOWER 25 ath5k.h  
63
AR5K_TUNE_TPC_TXPOWERAR5K_TUNE_TPC_TXPOWER 0 ath5k.h  
64
AR5K_TUNE_ANT_DIVERSITYAR5K_TUNE_ANT_DIVERSITY 1 ath5k.h  
65
AR5K_TUNE_HWTXTRIESAR5K_TUNE_HWTXTRIES 4 ath5k.h  
66
AR5K_INIT_CARR_SENSE_ENAR5K_INIT_CARR_SENSE_EN 1 ath5k.h  
67
AR5K_INIT_CFGAR5K_INIT_CFG ( \ AR5K_CFG_SWTD | AR5K_CFG_SWRD \ ) ath5k.h  
68
AR5K_INIT_CFGAR5K_INIT_CFG 0x00000000 ath5k.h  
69
AR5K_INIT_CYCRSSI_THR1AR5K_INIT_CYCRSSI_THR1 2 ath5k.h  
70
AR5K_INIT_TX_LATENCYAR5K_INIT_TX_LATENCY 502 ath5k.h  
71
AR5K_INIT_USECAR5K_INIT_USEC 39 ath5k.h  
72
AR5K_INIT_USEC_TURBOAR5K_INIT_USEC_TURBO 79 ath5k.h  
73
AR5K_INIT_USEC_32AR5K_INIT_USEC_32 31 ath5k.h  
74
AR5K_INIT_SLOT_TIMEAR5K_INIT_SLOT_TIME 396 ath5k.h  
75
AR5K_INIT_SLOT_TIME_TURBOAR5K_INIT_SLOT_TIME_TURBO 480 ath5k.h  
76
AR5K_INIT_ACK_CTS_TIMEOUTAR5K_INIT_ACK_CTS_TIMEOUT 1024 ath5k.h  
77
AR5K_INIT_ACK_CTS_TIMEOUT_TURBOAR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 ath5k.h  
78
AR5K_INIT_PROG_IFSAR5K_INIT_PROG_IFS 920 ath5k.h  
79
AR5K_INIT_PROG_IFS_TURBOAR5K_INIT_PROG_IFS_TURBO 960 ath5k.h  
80
AR5K_INIT_EIFSAR5K_INIT_EIFS 3440 ath5k.h  
81
AR5K_INIT_EIFS_TURBOAR5K_INIT_EIFS_TURBO 6880 ath5k.h  
82
AR5K_INIT_SIFSAR5K_INIT_SIFS 560 ath5k.h  
83
AR5K_INIT_SIFS_TURBOAR5K_INIT_SIFS_TURBO 480 ath5k.h  
84
AR5K_INIT_SH_RETRYAR5K_INIT_SH_RETRY 10 ath5k.h  
85
AR5K_INIT_LG_RETRYAR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY ath5k.h  
86
AR5K_INIT_SSH_RETRYAR5K_INIT_SSH_RETRY 32 ath5k.h  
87
AR5K_INIT_SLG_RETRYAR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY ath5k.h  
88
AR5K_INIT_TX_RETRYAR5K_INIT_TX_RETRY 10 ath5k.h  
89
AR5K_INIT_TRANSMIT_LATENCYAR5K_INIT_TRANSMIT_LATENCY ( \ (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ (AR5K_INIT_USEC) \ ) ath5k.h  
90
AR5K_INIT_TRANSMIT_LATENCY_TURBAR5K_INIT_TRANSMIT_LATENCY_TURB ( \ (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ (AR5K_INIT_USEC_TURBO) \ ) ath5k.h  
91
AR5K_INIT_PROTO_TIME_CNTRLAR5K_INIT_PROTO_TIME_CNTRL ( \ (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ (AR5K_INIT_PROG_IFS) \ ) ath5k.h  
92
AR5K_INIT_PROTO_TIME_CNTRL_TURBAR5K_INIT_PROTO_TIME_CNTRL_TURB ( \ (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ (AR5K_INIT_PROG_IFS_TURBO) \ ) ath5k.h  
93
AR5K_TXQ_USEDEFAULTAR5K_TXQ_USEDEFAULT ((u32) -1) ath5k.h  
94
AR5K_SREV_UNKNOWNAR5K_SREV_UNKNOWN 0xffff ath5k.h  
95
AR5K_SREV_AR5210AR5K_SREV_AR5210 0x00 ath5k.h Crete
96
AR5K_SREV_AR5311AR5K_SREV_AR5311 0x10 ath5k.h Maui 1
97
AR5K_SREV_AR5311AAR5K_SREV_AR5311A 0x20 ath5k.h Maui 2
98
AR5K_SREV_AR5311BAR5K_SREV_AR5311B 0x30 ath5k.h Spirit
99
AR5K_SREV_AR5211AR5K_SREV_AR5211 0x40 ath5k.h Oahu
100
AR5K_SREV_AR5212AR5K_SREV_AR5212 0x50 ath5k.h Venice
101
AR5K_SREV_AR5213AR5K_SREV_AR5213 0x55 ath5k.h ???
102
AR5K_SREV_AR5213AAR5K_SREV_AR5213A 0x59 ath5k.h Hainan
103
AR5K_SREV_AR2413AR5K_SREV_AR2413 0x78 ath5k.h Griffin lite
104
AR5K_SREV_AR2414AR5K_SREV_AR2414 0x70 ath5k.h Griffin
105
AR5K_SREV_AR5424AR5K_SREV_AR5424 0x90 ath5k.h Condor
106
AR5K_SREV_AR5413AR5K_SREV_AR5413 0xa4 ath5k.h Eagle lite
107
AR5K_SREV_AR5414AR5K_SREV_AR5414 0xa0 ath5k.h Eagle
108
AR5K_SREV_AR2415AR5K_SREV_AR2415 0xb0 ath5k.h Talon
109
AR5K_SREV_AR5416AR5K_SREV_AR5416 0xc0 ath5k.h PCI-E
110
AR5K_SREV_AR5418AR5K_SREV_AR5418 0xca ath5k.h PCI-E
111
AR5K_SREV_AR2425AR5K_SREV_AR2425 0xe0 ath5k.h Swan
112
AR5K_SREV_AR2417AR5K_SREV_AR2417 0xf0 ath5k.h Nala
113
AR5K_SREV_RAD_5110AR5K_SREV_RAD_5110 0x00 ath5k.h  
114
AR5K_SREV_RAD_5111AR5K_SREV_RAD_5111 0x10 ath5k.h  
115
AR5K_SREV_RAD_5111AAR5K_SREV_RAD_5111A 0x15 ath5k.h  
116
AR5K_SREV_RAD_2111AR5K_SREV_RAD_2111 0x20 ath5k.h  
117
AR5K_SREV_RAD_5112AR5K_SREV_RAD_5112 0x30 ath5k.h  
118
AR5K_SREV_RAD_5112AAR5K_SREV_RAD_5112A 0x35 ath5k.h  
119
AR5K_SREV_RAD_5112BAR5K_SREV_RAD_5112B 0x36 ath5k.h  
120
AR5K_SREV_RAD_2112AR5K_SREV_RAD_2112 0x40 ath5k.h  
121
AR5K_SREV_RAD_2112AAR5K_SREV_RAD_2112A 0x45 ath5k.h  
122
AR5K_SREV_RAD_2112BAR5K_SREV_RAD_2112B 0x46 ath5k.h  
123
AR5K_SREV_RAD_2413AR5K_SREV_RAD_2413 0x50 ath5k.h  
124
AR5K_SREV_RAD_5413AR5K_SREV_RAD_5413 0x60 ath5k.h  
125
AR5K_SREV_RAD_2316AR5K_SREV_RAD_2316 0x70 ath5k.h Cobra SoC
126
AR5K_SREV_RAD_2317AR5K_SREV_RAD_2317 0x80 ath5k.h  
127
AR5K_SREV_RAD_5424AR5K_SREV_RAD_5424 0xa0 ath5k.h Mostly same as 5413
128
AR5K_SREV_RAD_2425AR5K_SREV_RAD_2425 0xa2 ath5k.h  
129
AR5K_SREV_RAD_5133AR5K_SREV_RAD_5133 0xc0 ath5k.h  
130
AR5K_SREV_PHY_5211AR5K_SREV_PHY_5211 0x30 ath5k.h  
131
AR5K_SREV_PHY_5212AR5K_SREV_PHY_5212 0x41 ath5k.h  
132
AR5K_SREV_PHY_5212AAR5K_SREV_PHY_5212A 0x42 ath5k.h  
133
AR5K_SREV_PHY_5212BAR5K_SREV_PHY_5212B 0x43 ath5k.h  
134
AR5K_SREV_PHY_2413AR5K_SREV_PHY_2413 0x45 ath5k.h  
135
AR5K_SREV_PHY_5413AR5K_SREV_PHY_5413 0x61 ath5k.h  
136
AR5K_SREV_PHY_2425AR5K_SREV_PHY_2425 0x70 ath5k.h  
137
MODULATION_XRMODULATION_XR 0x00000200 ath5k.h  
138
MODULATION_TURBOMODULATION_TURBO 0x00000080 ath5k.h  
139
AR5K_TXSTAT_ALTRATEAR5K_TXSTAT_ALTRATE 0x80 ath5k.h  
140
AR5K_TXERR_XRETRYAR5K_TXERR_XRETRY 0x01 ath5k.h  
141
AR5K_TXERR_FILTAR5K_TXERR_FILT 0x02 ath5k.h  
142
AR5K_TXERR_FIFOAR5K_TXERR_FIFO 0x04 ath5k.h  
143
AR5K_TXQ_FLAG_TXOKINT_ENABLEAR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 ath5k.h Enable TXOK interrupt
144
AR5K_TXQ_FLAG_TXERRINT_ENABLEAR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 ath5k.h Enable TXERR interrupt
145
AR5K_TXQ_FLAG_TXEOLINT_ENABLEAR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 ath5k.h Enable TXEOL interrupt -not used-
146
AR5K_TXQ_FLAG_TXDESCINT_ENABLEAR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 ath5k.h Enable TXDESC interrupt -not used-
147
AR5K_TXQ_FLAG_TXURNINT_ENABLEAR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 ath5k.h Enable TXURN interrupt
148
AR5K_TXQ_FLAG_CBRORNINT_ENABLEAR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 ath5k.h Enable CBRORN interrupt
149
AR5K_TXQ_FLAG_CBRURNINT_ENABLEAR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 ath5k.h Enable CBRURN interrupt
150
AR5K_TXQ_FLAG_QTRIGINT_ENABLEAR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 ath5k.h Enable QTRIG interrupt
151
AR5K_TXQ_FLAG_TXNOFRMINT_ENABLEAR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 ath5k.h Enable TXNOFRM interrupt
152
AR5K_TXQ_FLAG_BACKOFF_DISABLEAR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 ath5k.h Disable random post-backoff
153
AR5K_TXQ_FLAG_RDYTIME_EXP_POLICAR5K_TXQ_FLAG_RDYTIME_EXP_POLIC 0x0300 ath5k.h Enable ready time expiry policy (?)
154
AR5K_TXQ_FLAG_FRAG_BURST_BACKOFAR5K_TXQ_FLAG_FRAG_BURST_BACKOF 0x0800 ath5k.h Enable backoff while bursting
155
AR5K_TXQ_FLAG_POST_FR_BKOFF_DISAR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 ath5k.h Disable backoff while bursting
156
AR5K_TXQ_FLAG_COMPRESSION_ENABLAR5K_TXQ_FLAG_COMPRESSION_ENABL 0x2000 ath5k.h Enable hw compression -not implemented-
157
AR5K_RXERR_CRCAR5K_RXERR_CRC 0x01 ath5k.h  
158
AR5K_RXERR_PHYAR5K_RXERR_PHY 0x02 ath5k.h  
159
AR5K_RXERR_FIFOAR5K_RXERR_FIFO 0x04 ath5k.h  
160
AR5K_RXERR_DECRYPTAR5K_RXERR_DECRYPT 0x08 ath5k.h  
161
AR5K_RXERR_MICAR5K_RXERR_MIC 0x10 ath5k.h  
162
AR5K_RXKEYIX_INVALIDAR5K_RXKEYIX_INVALID ((u8) - 1) ath5k.h  
163
AR5K_TXKEYIX_INVALIDAR5K_TXKEYIX_INVALID ((u32) - 1) ath5k.h  
164
AR5K_SLOT_TIME_9AR5K_SLOT_TIME_9 396 ath5k.h  
165
AR5K_SLOT_TIME_20AR5K_SLOT_TIME_20 880 ath5k.h  
166
AR5K_SLOT_TIME_MAXAR5K_SLOT_TIME_MAX 0xffff ath5k.h  
167
CHANNEL_CW_INTCHANNEL_CW_INT 0x0008 ath5k.h Contention Window interference detected
168
CHANNEL_TURBOCHANNEL_TURBO 0x0010 ath5k.h Turbo Channel
169
CHANNEL_CCKCHANNEL_CCK 0x0020 ath5k.h CCK channel
170
CHANNEL_OFDMCHANNEL_OFDM 0x0040 ath5k.h OFDM channel
171
CHANNEL_2GHZCHANNEL_2GHZ 0x0080 ath5k.h 2GHz channel.
172
CHANNEL_5GHZCHANNEL_5GHZ 0x0100 ath5k.h 5GHz channel
173
CHANNEL_PASSIVECHANNEL_PASSIVE 0x0200 ath5k.h Only passive scan allowed
174
CHANNEL_DYNCHANNEL_DYN 0x0400 ath5k.h Dynamic CCK-OFDM channel (for g operation)
175
CHANNEL_XRCHANNEL_XR 0x0800 ath5k.h XR channel
176
CHANNEL_ACHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) ath5k.h  
177
CHANNEL_BCHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) ath5k.h  
178
CHANNEL_GCHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) ath5k.h  
179
CHANNEL_TCHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) ath5k.h  
180
CHANNEL_TGCHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) ath5k.h  
181
CHANNEL_108ACHANNEL_108A CHANNEL_T ath5k.h  
182
CHANNEL_108GCHANNEL_108G CHANNEL_TG ath5k.h  
183
CHANNEL_XCHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) ath5k.h  
184
CHANNEL_ALLCHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \ CHANNEL_TURBO) ath5k.h  
185
CHANNEL_ALL_NOTURBOCHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) ath5k.h  
186
CHANNEL_MODESCHANNEL_MODES CHANNEL_ALL ath5k.h  
187
AR5K_MAX_RATESAR5K_MAX_RATES 32 ath5k.h  
188
ATH5K_RATE_CODE_1MATH5K_RATE_CODE_1M 0x1B ath5k.h  
189
ATH5K_RATE_CODE_2MATH5K_RATE_CODE_2M 0x1A ath5k.h  
190
ATH5K_RATE_CODE_5_5MATH5K_RATE_CODE_5_5M 0x19 ath5k.h  
191
ATH5K_RATE_CODE_11MATH5K_RATE_CODE_11M 0x18 ath5k.h  
192
ATH5K_RATE_CODE_6MATH5K_RATE_CODE_6M 0x0B ath5k.h  
193
ATH5K_RATE_CODE_9MATH5K_RATE_CODE_9M 0x0F ath5k.h  
194
ATH5K_RATE_CODE_12MATH5K_RATE_CODE_12M 0x0A ath5k.h  
195
ATH5K_RATE_CODE_18MATH5K_RATE_CODE_18M 0x0E ath5k.h  
196
ATH5K_RATE_CODE_24MATH5K_RATE_CODE_24M 0x09 ath5k.h  
197
ATH5K_RATE_CODE_36MATH5K_RATE_CODE_36M 0x0D ath5k.h  
198
ATH5K_RATE_CODE_48MATH5K_RATE_CODE_48M 0x08 ath5k.h  
199
ATH5K_RATE_CODE_54MATH5K_RATE_CODE_54M 0x0C ath5k.h  
200
ATH5K_RATE_CODE_XR_500KATH5K_RATE_CODE_XR_500K 0x07 ath5k.h  
201
ATH5K_RATE_CODE_XR_1MATH5K_RATE_CODE_XR_1M 0x02 ath5k.h  
202
ATH5K_RATE_CODE_XR_2MATH5K_RATE_CODE_XR_2M 0x06 ath5k.h  
203
ATH5K_RATE_CODE_XR_3MATH5K_RATE_CODE_XR_3M 0x01 ath5k.h  
204
AR5K_SET_SHORT_PREAMBLEAR5K_SET_SHORT_PREAMBLE 0x04 ath5k.h  
205
AR5K_KEYCACHE_SIZEAR5K_KEYCACHE_SIZE 8 ath5k.h  
206
AR5K_RSSI_EP_MULTIPLIERAR5K_RSSI_EP_MULTIPLIER (1<<7) ath5k.h  
207
AR5K_SOFTLED_PINAR5K_SOFTLED_PIN 0 ath5k.h  
208
AR5K_SOFTLED_ONAR5K_SOFTLED_ON 0 ath5k.h  
209
AR5K_SOFTLED_OFFAR5K_SOFTLED_OFF 1 ath5k.h  
210
AR5K_MAX_GPIOAR5K_MAX_GPIO 10 ath5k.h  
211
AR5K_MAX_RF_BANKSAR5K_MAX_RF_BANKS 8 ath5k.h  
212
ATH_RXBUFATH_RXBUF 16 base.h number of RX buffers
213
ATH_TXBUFATH_TXBUF 16 base.h number of TX buffers
214
ATH_CHAN_MAXATH_CHAN_MAX (26+26+26+200+200) base.h  
215
ATH_CHAN_MAXATH_CHAN_MAX (14+14+14+252+20) base.h  
216
AR5K_DESC_RX_CTL0AR5K_DESC_RX_CTL0 0x00000000 desc.h  
217
AR5K_DESC_RX_CTL1_BUF_LENAR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff desc.h  
218
AR5K_DESC_RX_CTL1_INTREQAR5K_DESC_RX_CTL1_INTREQ 0x00002000 desc.h  
219
AR5K_5210_RX_DESC_STATUS0_DATA_AR5K_5210_RX_DESC_STATUS0_DATA_ 0x00000fff desc.h  
220
AR5K_5210_RX_DESC_STATUS0_MOREAR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 desc.h  
221
AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 0x00078000 desc.h  
222
AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 15 desc.h  
223
AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 0x07f80000 desc.h  
224
AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 19 desc.h  
225
AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 0x38000000 desc.h  
226
AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 27 desc.h  
227
AR5K_5210_RX_DESC_STATUS1_DONEAR5K_5210_RX_DESC_STATUS1_DONE 0x00000001 desc.h  
228
AR5K_5210_RX_DESC_STATUS1_FRAMEAR5K_5210_RX_DESC_STATUS1_FRAME 0x00000002 desc.h  
229
AR5K_5210_RX_DESC_STATUS1_CRC_EAR5K_5210_RX_DESC_STATUS1_CRC_E 0x00000004 desc.h  
230
AR5K_5210_RX_DESC_STATUS1_FIFO_AR5K_5210_RX_DESC_STATUS1_FIFO_ 0x00000008 desc.h  
231
AR5K_5210_RX_DESC_STATUS1_DECRYAR5K_5210_RX_DESC_STATUS1_DECRY 0x00000010 desc.h  
232
AR5K_5210_RX_DESC_STATUS1_PHY_EAR5K_5210_RX_DESC_STATUS1_PHY_E 0x000000e0 desc.h  
233
AR5K_5210_RX_DESC_STATUS1_PHY_EAR5K_5210_RX_DESC_STATUS1_PHY_E 5 desc.h  
234
AR5K_5210_RX_DESC_STATUS1_KEY_IAR5K_5210_RX_DESC_STATUS1_KEY_I 0x00000100 desc.h  
235
AR5K_5210_RX_DESC_STATUS1_KEY_IAR5K_5210_RX_DESC_STATUS1_KEY_I 0x00007e00 desc.h  
236
AR5K_5210_RX_DESC_STATUS1_KEY_IAR5K_5210_RX_DESC_STATUS1_KEY_I 9 desc.h  
237
AR5K_5210_RX_DESC_STATUS1_RECEIAR5K_5210_RX_DESC_STATUS1_RECEI 0x0fff8000 desc.h  
238
AR5K_5210_RX_DESC_STATUS1_RECEIAR5K_5210_RX_DESC_STATUS1_RECEI 15 desc.h  
239
AR5K_5210_RX_DESC_STATUS1_KEY_CAR5K_5210_RX_DESC_STATUS1_KEY_C 0x10000000 desc.h  
240
AR5K_5212_RX_DESC_STATUS0_DATA_AR5K_5212_RX_DESC_STATUS0_DATA_ 0x00000fff desc.h  
241
AR5K_5212_RX_DESC_STATUS0_MOREAR5K_5212_RX_DESC_STATUS0_MORE 0x00001000 desc.h  
242
AR5K_5212_RX_DESC_STATUS0_DECOMAR5K_5212_RX_DESC_STATUS0_DECOM 0x00002000 desc.h  
243
AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 0x000f8000 desc.h  
244
AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 15 desc.h  
245
AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 0x0ff00000 desc.h  
246
AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 20 desc.h  
247
AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 0xf0000000 desc.h  
248
AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 28 desc.h  
249
AR5K_5212_RX_DESC_STATUS1_DONEAR5K_5212_RX_DESC_STATUS1_DONE 0x00000001 desc.h  
250
AR5K_5212_RX_DESC_STATUS1_FRAMEAR5K_5212_RX_DESC_STATUS1_FRAME 0x00000002 desc.h  
251
AR5K_5212_RX_DESC_STATUS1_CRC_EAR5K_5212_RX_DESC_STATUS1_CRC_E 0x00000004 desc.h  
252
AR5K_5212_RX_DESC_STATUS1_DECRYAR5K_5212_RX_DESC_STATUS1_DECRY 0x00000008 desc.h  
253
AR5K_5212_RX_DESC_STATUS1_PHY_EAR5K_5212_RX_DESC_STATUS1_PHY_E 0x00000010 desc.h  
254
AR5K_5212_RX_DESC_STATUS1_MIC_EAR5K_5212_RX_DESC_STATUS1_MIC_E 0x00000020 desc.h  
255
AR5K_5212_RX_DESC_STATUS1_KEY_IAR5K_5212_RX_DESC_STATUS1_KEY_I 0x00000100 desc.h  
256
AR5K_5212_RX_DESC_STATUS1_KEY_IAR5K_5212_RX_DESC_STATUS1_KEY_I 0x0000fe00 desc.h  
257
AR5K_5212_RX_DESC_STATUS1_KEY_IAR5K_5212_RX_DESC_STATUS1_KEY_I 9 desc.h  
258
AR5K_5212_RX_DESC_STATUS1_RECEIAR5K_5212_RX_DESC_STATUS1_RECEI 0x7fff0000 desc.h  
259
AR5K_5212_RX_DESC_STATUS1_RECEIAR5K_5212_RX_DESC_STATUS1_RECEI 16 desc.h  
260
AR5K_5212_RX_DESC_STATUS1_KEY_CAR5K_5212_RX_DESC_STATUS1_KEY_C 0x80000000 desc.h  
261
AR5K_RX_DESC_ERROR0AR5K_RX_DESC_ERROR0 0x00000000 desc.h  
262
AR5K_RX_DESC_ERROR1_PHY_ERROR_CAR5K_RX_DESC_ERROR1_PHY_ERROR_C 0x0000ff00 desc.h  
263
AR5K_RX_DESC_ERROR1_PHY_ERROR_CAR5K_RX_DESC_ERROR1_PHY_ERROR_C 8 desc.h  
264
AR5K_DESC_RX_PHY_ERROR_NONEAR5K_DESC_RX_PHY_ERROR_NONE 0x00 desc.h  
265
AR5K_DESC_RX_PHY_ERROR_TIMINGAR5K_DESC_RX_PHY_ERROR_TIMING 0x20 desc.h  
266
AR5K_DESC_RX_PHY_ERROR_PARITYAR5K_DESC_RX_PHY_ERROR_PARITY 0x40 desc.h  
267
AR5K_DESC_RX_PHY_ERROR_RATEAR5K_DESC_RX_PHY_ERROR_RATE 0x60 desc.h  
268
AR5K_DESC_RX_PHY_ERROR_LENGTHAR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 desc.h  
269
AR5K_DESC_RX_PHY_ERROR_64QAMAR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 desc.h  
270
AR5K_DESC_RX_PHY_ERROR_SERVICEAR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 desc.h  
271
AR5K_DESC_RX_PHY_ERROR_TRANSMITAR5K_DESC_RX_PHY_ERROR_TRANSMIT 0xe0 desc.h  
272
AR5K_2W_TX_DESC_CTL0_FRAME_LENAR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff desc.h  
273
AR5K_2W_TX_DESC_CTL0_HEADER_LENAR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 desc.h [5210 ?]
274
AR5K_2W_TX_DESC_CTL0_HEADER_LENAR5K_2W_TX_DESC_CTL0_HEADER_LEN 12 desc.h  
275
AR5K_2W_TX_DESC_CTL0_XMIT_RATEAR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 desc.h  
276
AR5K_2W_TX_DESC_CTL0_XMIT_RATE_AR5K_2W_TX_DESC_CTL0_XMIT_RATE_ 18 desc.h  
277
AR5K_2W_TX_DESC_CTL0_RTSENAAR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 desc.h  
278
AR5K_2W_TX_DESC_CTL0_CLRDMASKAR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 desc.h  
279
AR5K_2W_TX_DESC_CTL0_LONG_PACKEAR5K_2W_TX_DESC_CTL0_LONG_PACKE 0x00800000 desc.h [5210]
280
AR5K_2W_TX_DESC_CTL0_VEOLAR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 desc.h [5211]
281
AR5K_2W_TX_DESC_CTL0_FRAME_TYPEAR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 desc.h [5210]
282
AR5K_2W_TX_DESC_CTL0_FRAME_TYPEAR5K_2W_TX_DESC_CTL0_FRAME_TYPE 26 desc.h  
283
AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X 0x02000000 desc.h  
284
AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X 0x1e000000 desc.h  
285
AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X (ah->ah_version == AR5K_AR5210 ? \ AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) desc.h  
286
AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X 25 desc.h  
287
AR5K_2W_TX_DESC_CTL0_INTREQAR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 desc.h  
288
AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEAR5K_2W_TX_DESC_CTL0_ENCRYPT_KE 0x40000000 desc.h  
289
AR5K_2W_TX_DESC_CTL1_BUF_LENAR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff desc.h  
290
AR5K_2W_TX_DESC_CTL1_MOREAR5K_2W_TX_DESC_CTL1_MORE 0x00001000 desc.h  
291
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE 0x0007e000 desc.h  
292
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE 0x000fe000 desc.h  
293
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE (ah->ah_version == AR5K_AR5210 ? \ AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_52 desc.h  
294
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE 13 desc.h  
295
AR5K_2W_TX_DESC_CTL1_FRAME_TYPEAR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 desc.h [5211]
296
AR5K_2W_TX_DESC_CTL1_FRAME_TYPEAR5K_2W_TX_DESC_CTL1_FRAME_TYPE 20 desc.h  
297
AR5K_2W_TX_DESC_CTL1_NOACKAR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 desc.h [5211]
298
AR5K_2W_TX_DESC_CTL1_RTS_DURATIAR5K_2W_TX_DESC_CTL1_RTS_DURATI 0xfff80000 desc.h [5210 ?]
299
AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x00 desc.h  
300
AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x04 desc.h  
301
AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x08 desc.h  
302
AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x0c desc.h  
303
AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x10 desc.h  
304
AR5K_DESC_TX_STATUS0_FRAME_XMITAR5K_DESC_TX_STATUS0_FRAME_XMIT 0x00000001 desc.h  
305
AR5K_DESC_TX_STATUS0_EXCESSIVE_AR5K_DESC_TX_STATUS0_EXCESSIVE_ 0x00000002 desc.h  
306
AR5K_DESC_TX_STATUS0_FIFO_UNDERAR5K_DESC_TX_STATUS0_FIFO_UNDER 0x00000004 desc.h  
307
AR5K_DESC_TX_STATUS0_FILTEREDAR5K_DESC_TX_STATUS0_FILTERED 0x00000008 desc.h  
308
AR5K_DESC_TX_STATUS0_SHORT_RETRAR5K_DESC_TX_STATUS0_SHORT_RETR 0x000000f0 desc.h  
309
AR5K_DESC_TX_STATUS0_SHORT_RETRAR5K_DESC_TX_STATUS0_SHORT_RETR 4 desc.h  
310
AR5K_DESC_TX_STATUS0_LONG_RETRYAR5K_DESC_TX_STATUS0_LONG_RETRY 0x00000f00 desc.h  
311
AR5K_DESC_TX_STATUS0_LONG_RETRYAR5K_DESC_TX_STATUS0_LONG_RETRY 8 desc.h  
312
AR5K_DESC_TX_STATUS0_VIRT_COLL_AR5K_DESC_TX_STATUS0_VIRT_COLL_ 0x0000f000 desc.h  
313
AR5K_DESC_TX_STATUS0_VIRT_COLL_AR5K_DESC_TX_STATUS0_VIRT_COLL_ 12 desc.h  
314
AR5K_DESC_TX_STATUS0_SEND_TIMESAR5K_DESC_TX_STATUS0_SEND_TIMES 0xffff0000 desc.h  
315
AR5K_DESC_TX_STATUS0_SEND_TIMESAR5K_DESC_TX_STATUS0_SEND_TIMES 16 desc.h  
316
AR5K_DESC_TX_STATUS1_DONEAR5K_DESC_TX_STATUS1_DONE 0x00000001 desc.h  
317
AR5K_DESC_TX_STATUS1_SEQ_NUMAR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe desc.h  
318
AR5K_DESC_TX_STATUS1_SEQ_NUM_SAR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 desc.h  
319
AR5K_DESC_TX_STATUS1_ACK_SIG_STAR5K_DESC_TX_STATUS1_ACK_SIG_ST 0x001fe000 desc.h  
320
AR5K_DESC_TX_STATUS1_ACK_SIG_STAR5K_DESC_TX_STATUS1_ACK_SIG_ST 13 desc.h  
321
AR5K_DESC_TX_STATUS1_FINAL_TS_IAR5K_DESC_TX_STATUS1_FINAL_TS_I 0x00600000 desc.h  
322
AR5K_DESC_TX_STATUS1_FINAL_TS_IAR5K_DESC_TX_STATUS1_FINAL_TS_I 21 desc.h  
323
AR5K_DESC_TX_STATUS1_COMP_SUCCEAR5K_DESC_TX_STATUS1_COMP_SUCCE 0x00800000 desc.h  
324
AR5K_DESC_TX_STATUS1_XMIT_ANTENAR5K_DESC_TX_STATUS1_XMIT_ANTEN 0x01000000 desc.h  
325
AR5K_RXDESC_INTREQAR5K_RXDESC_INTREQ 0x0020 desc.h  
326
AR5K_TXDESC_CLRDMASKAR5K_TXDESC_CLRDMASK 0x0001 desc.h  
327
AR5K_TXDESC_NOACKAR5K_TXDESC_NOACK 0x0002 desc.h [5211+]
328
AR5K_TXDESC_RTSENAAR5K_TXDESC_RTSENA 0x0004 desc.h  
329
AR5K_TXDESC_CTSENAAR5K_TXDESC_CTSENA 0x0008 desc.h  
330
AR5K_TXDESC_INTREQAR5K_TXDESC_INTREQ 0x0010 desc.h  
331
AR5K_TXDESC_VEOLAR5K_TXDESC_VEOL 0x0020 desc.h [5211+]
332
AR5K_EEPROM_MAGICAR5K_EEPROM_MAGIC 0x003d eeprom.h EEPROM Magic number
333
AR5K_EEPROM_MAGIC_VALUEAR5K_EEPROM_MAGIC_VALUE 0x5aa5 eeprom.h Default - found on EEPROM
334
AR5K_EEPROM_MAGIC_5212AR5K_EEPROM_MAGIC_5212 0x0000145c eeprom.h 5212
335
AR5K_EEPROM_MAGIC_5211AR5K_EEPROM_MAGIC_5211 0x0000145b eeprom.h 5211
336
AR5K_EEPROM_MAGIC_5210AR5K_EEPROM_MAGIC_5210 0x0000145a eeprom.h 5210
337
AR5K_EEPROM_IS_HB63AR5K_EEPROM_IS_HB63 0x000b eeprom.h Talon detect
338
AR5K_EEPROM_RFKILLAR5K_EEPROM_RFKILL 0x0f eeprom.h  
339
AR5K_EEPROM_RFKILL_GPIO_SELAR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c eeprom.h  
340
AR5K_EEPROM_RFKILL_GPIO_SEL_SAR5K_EEPROM_RFKILL_GPIO_SEL_S 2 eeprom.h  
341
AR5K_EEPROM_RFKILL_POLARITYAR5K_EEPROM_RFKILL_POLARITY 0x00000002 eeprom.h  
342
AR5K_EEPROM_RFKILL_POLARITY_SAR5K_EEPROM_RFKILL_POLARITY_S 1 eeprom.h  
343
AR5K_EEPROM_REG_DOMAINAR5K_EEPROM_REG_DOMAIN 0x00bf eeprom.h EEPROM regdom
344
AR5K_EEPROM_CHECKSUMAR5K_EEPROM_CHECKSUM 0x00c0 eeprom.h EEPROM checksum
345
AR5K_EEPROM_INFO_BASEAR5K_EEPROM_INFO_BASE 0x00c0 eeprom.h EEPROM header
346
AR5K_EEPROM_INFO_MAXAR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) eeprom.h  
347
AR5K_EEPROM_INFO_CKSUMAR5K_EEPROM_INFO_CKSUM 0xffff eeprom.h  
348
AR5K_EEPROM_VERSIONAR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) eeprom.h EEPROM Version
349
AR5K_EEPROM_VERSION_3_0AR5K_EEPROM_VERSION_3_0 0x3000 eeprom.h No idea what's going on before this version
350
AR5K_EEPROM_VERSION_3_1AR5K_EEPROM_VERSION_3_1 0x3001 eeprom.h ob/db values for 2Ghz (ar5211_rfregs)
351
AR5K_EEPROM_VERSION_3_2AR5K_EEPROM_VERSION_3_2 0x3002 eeprom.h different frequency representation (eeprom_bin2freq)
352
AR5K_EEPROM_VERSION_3_3AR5K_EEPROM_VERSION_3_3 0x3003 eeprom.h offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes)
353
AR5K_EEPROM_VERSION_3_4AR5K_EEPROM_VERSION_3_4 0x3004 eeprom.h has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes)
354
AR5K_EEPROM_VERSION_4_0AR5K_EEPROM_VERSION_4_0 0x4000 eeprom.h has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init)
355
AR5K_EEPROM_VERSION_4_1AR5K_EEPROM_VERSION_4_1 0x4001 eeprom.h has ee_margin_tx_rx (eeprom_init)
356
AR5K_EEPROM_VERSION_4_2AR5K_EEPROM_VERSION_4_2 0x4002 eeprom.h has ee_cck_ofdm_gain_delta (eeprom_init)
357
AR5K_EEPROM_VERSION_4_3AR5K_EEPROM_VERSION_4_3 0x4003 eeprom.h power calibration changes
358
AR5K_EEPROM_VERSION_4_4AR5K_EEPROM_VERSION_4_4 0x4004 eeprom.h  
359
AR5K_EEPROM_VERSION_4_5AR5K_EEPROM_VERSION_4_5 0x4005 eeprom.h  
360
AR5K_EEPROM_VERSION_4_6AR5K_EEPROM_VERSION_4_6 0x4006 eeprom.h has ee_scaled_cck_delta
361
AR5K_EEPROM_VERSION_4_7AR5K_EEPROM_VERSION_4_7 0x3007 eeprom.h 4007 ?
362
AR5K_EEPROM_VERSION_4_9AR5K_EEPROM_VERSION_4_9 0x4009 eeprom.h EAR futureproofing
363
AR5K_EEPROM_VERSION_5_0AR5K_EEPROM_VERSION_5_0 0x5000 eeprom.h Has 2413 PDADC calibration etc
364
AR5K_EEPROM_VERSION_5_1AR5K_EEPROM_VERSION_5_1 0x5001 eeprom.h Has capability values
365
AR5K_EEPROM_VERSION_5_3AR5K_EEPROM_VERSION_5_3 0x5003 eeprom.h Has spur mitigation tables
366
AR5K_EEPROM_MODE_11AAR5K_EEPROM_MODE_11A 0 eeprom.h  
367
AR5K_EEPROM_MODE_11BAR5K_EEPROM_MODE_11B 1 eeprom.h  
368
AR5K_EEPROM_MODE_11GAR5K_EEPROM_MODE_11G 2 eeprom.h  
369
AR5K_EEPROM_HDRAR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) eeprom.h Header that contains the device caps
370
AR5K_EEPROM_RFKILL_GPIO_SELAR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c eeprom.h  
371
AR5K_EEPROM_RFKILL_GPIO_SEL_SAR5K_EEPROM_RFKILL_GPIO_SEL_S 2 eeprom.h  
372
AR5K_EEPROM_RFKILL_POLARITYAR5K_EEPROM_RFKILL_POLARITY 0x00000002 eeprom.h  
373
AR5K_EEPROM_RFKILL_POLARITY_SAR5K_EEPROM_RFKILL_POLARITY_S 1 eeprom.h  
374
AR5K_EEPROM_MISC0AR5K_EEPROM_MISC0 AR5K_EEPROM_INFO(4) eeprom.h  
375
AR5K_EEPROM_MISC1AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5) eeprom.h  
376
AR5K_EEPROM_MISC2AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6) eeprom.h  
377
AR5K_EEPROM_MISC3AR5K_EEPROM_MISC3 AR5K_EEPROM_INFO(7) eeprom.h  
378
AR5K_EEPROM_MISC4AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8) eeprom.h  
379
AR5K_EEPROM_MISC5AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9) eeprom.h  
380
AR5K_EEPROM_MISC6AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10) eeprom.h  
381
AR5K_EEPROM_TX_CHAIN_DISAR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8) eeprom.h  
382
AR5K_EEPROM_RX_CHAIN_DISAR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8) eeprom.h  
383
AR5K_EEPROM_FCC_MID_ENAR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) eeprom.h  
384
AR5K_EEPROM_JAP_U1EVEN_ENAR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) eeprom.h  
385
AR5K_EEPROM_JAP_U2_ENAR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) eeprom.h  
386
AR5K_EEPROM_JAP_U1ODD_ENAR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1) eeprom.h  
387
AR5K_EEPROM_JAP_11A_NEW_ENAR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1) eeprom.h  
388
AR5K_EEPROM_GROUP1_OFFSETAR5K_EEPROM_GROUP1_OFFSET 0x0 eeprom.h  
389
AR5K_EEPROM_GROUP2_OFFSETAR5K_EEPROM_GROUP2_OFFSET 0x5 eeprom.h  
390
AR5K_EEPROM_GROUP3_OFFSETAR5K_EEPROM_GROUP3_OFFSET 0x37 eeprom.h  
391
AR5K_EEPROM_GROUP4_OFFSETAR5K_EEPROM_GROUP4_OFFSET 0x46 eeprom.h  
392
AR5K_EEPROM_GROUP5_OFFSETAR5K_EEPROM_GROUP5_OFFSET 0x55 eeprom.h  
393
AR5K_EEPROM_GROUP6_OFFSETAR5K_EEPROM_GROUP6_OFFSET 0x65 eeprom.h  
394
AR5K_EEPROM_GROUP7_OFFSETAR5K_EEPROM_GROUP7_OFFSET 0x69 eeprom.h  
395
AR5K_EEPROM_GROUP8_OFFSETAR5K_EEPROM_GROUP8_OFFSET 0x6f eeprom.h  
396
AR5K_EEPROM_OBDB0_2GHZAR5K_EEPROM_OBDB0_2GHZ 0x00ec eeprom.h  
397
AR5K_EEPROM_OBDB1_2GHZAR5K_EEPROM_OBDB1_2GHZ 0x00ed eeprom.h  
398
AR5K_EEPROM_PROTECTAR5K_EEPROM_PROTECT 0x003f eeprom.h EEPROM protect status
399
AR5K_EEPROM_PROTECT_RD_0_31AR5K_EEPROM_PROTECT_RD_0_31 0x0001 eeprom.h Read protection bit for offsets 0x0 - 0x1f
400
AR5K_EEPROM_PROTECT_WR_0_31AR5K_EEPROM_PROTECT_WR_0_31 0x0002 eeprom.h Write protection bit for offsets 0x0 - 0x1f
401
AR5K_EEPROM_PROTECT_RD_32_63AR5K_EEPROM_PROTECT_RD_32_63 0x0004 eeprom.h 0x20 - 0x3f
402
AR5K_EEPROM_PROTECT_WR_32_63AR5K_EEPROM_PROTECT_WR_32_63 0x0008 eeprom.h  
403
AR5K_EEPROM_PROTECT_RD_64_127AR5K_EEPROM_PROTECT_RD_64_127 0x0010 eeprom.h 0x40 - 0x7f
404
AR5K_EEPROM_PROTECT_WR_64_127AR5K_EEPROM_PROTECT_WR_64_127 0x0020 eeprom.h  
405
AR5K_EEPROM_PROTECT_RD_128_191AR5K_EEPROM_PROTECT_RD_128_191 0x0040 eeprom.h 0x80 - 0xbf (regdom)
406
AR5K_EEPROM_PROTECT_WR_128_191AR5K_EEPROM_PROTECT_WR_128_191 0x0080 eeprom.h  
407
AR5K_EEPROM_PROTECT_RD_192_207AR5K_EEPROM_PROTECT_RD_192_207 0x0100 eeprom.h 0xc0 - 0xcf
408
AR5K_EEPROM_PROTECT_WR_192_207AR5K_EEPROM_PROTECT_WR_192_207 0x0200 eeprom.h  
409
AR5K_EEPROM_PROTECT_RD_208_223AR5K_EEPROM_PROTECT_RD_208_223 0x0400 eeprom.h 0xd0 - 0xdf
410
AR5K_EEPROM_PROTECT_WR_208_223AR5K_EEPROM_PROTECT_WR_208_223 0x0800 eeprom.h  
411
AR5K_EEPROM_PROTECT_RD_224_239AR5K_EEPROM_PROTECT_RD_224_239 0x1000 eeprom.h 0xe0 - 0xef
412
AR5K_EEPROM_PROTECT_WR_224_239AR5K_EEPROM_PROTECT_WR_224_239 0x2000 eeprom.h  
413
AR5K_EEPROM_PROTECT_RD_240_255AR5K_EEPROM_PROTECT_RD_240_255 0x4000 eeprom.h 0xf0 - 0xff
414
AR5K_EEPROM_PROTECT_WR_240_255AR5K_EEPROM_PROTECT_WR_240_255 0x8000 eeprom.h  
415
AR5K_EEPROM_EEP_SCALEAR5K_EEPROM_EEP_SCALE 100 eeprom.h  
416
AR5K_EEPROM_EEP_DELTAAR5K_EEPROM_EEP_DELTA 10 eeprom.h  
417
AR5K_EEPROM_N_MODESAR5K_EEPROM_N_MODES 3 eeprom.h  
418
AR5K_EEPROM_N_5GHZ_CHANAR5K_EEPROM_N_5GHZ_CHAN 10 eeprom.h  
419
AR5K_EEPROM_N_2GHZ_CHANAR5K_EEPROM_N_2GHZ_CHAN 3 eeprom.h  
420
AR5K_EEPROM_N_2GHZ_CHAN_2413AR5K_EEPROM_N_2GHZ_CHAN_2413 4 eeprom.h  
421
AR5K_EEPROM_N_2GHZ_CHAN_MAXAR5K_EEPROM_N_2GHZ_CHAN_MAX 4 eeprom.h  
422
AR5K_EEPROM_MAX_CHANAR5K_EEPROM_MAX_CHAN 10 eeprom.h  
423
AR5K_EEPROM_N_PWR_POINTS_5111AR5K_EEPROM_N_PWR_POINTS_5111 11 eeprom.h  
424
AR5K_EEPROM_N_PCDACAR5K_EEPROM_N_PCDAC 11 eeprom.h  
425
AR5K_EEPROM_N_PHASE_CALAR5K_EEPROM_N_PHASE_CAL 5 eeprom.h  
426
AR5K_EEPROM_N_TEST_FREQAR5K_EEPROM_N_TEST_FREQ 8 eeprom.h  
427
AR5K_EEPROM_N_EDGESAR5K_EEPROM_N_EDGES 8 eeprom.h  
428
AR5K_EEPROM_N_INTERCEPTSAR5K_EEPROM_N_INTERCEPTS 11 eeprom.h  
429
AR5K_EEPROM_PCDAC_MAR5K_EEPROM_PCDAC_M 0x3f eeprom.h  
430
AR5K_EEPROM_PCDAC_STARTAR5K_EEPROM_PCDAC_START 1 eeprom.h  
431
AR5K_EEPROM_PCDAC_STOPAR5K_EEPROM_PCDAC_STOP 63 eeprom.h  
432
AR5K_EEPROM_PCDAC_STEPAR5K_EEPROM_PCDAC_STEP 1 eeprom.h  
433
AR5K_EEPROM_NON_EDGE_MAR5K_EEPROM_NON_EDGE_M 0x40 eeprom.h  
434
AR5K_EEPROM_CHANNEL_POWERAR5K_EEPROM_CHANNEL_POWER 8 eeprom.h  
435
AR5K_EEPROM_N_OBDBAR5K_EEPROM_N_OBDB 4 eeprom.h  
436
AR5K_EEPROM_OBDB_DISAR5K_EEPROM_OBDB_DIS 0xffff eeprom.h  
437
AR5K_EEPROM_CHANNEL_DISAR5K_EEPROM_CHANNEL_DIS 0xff eeprom.h  
438
AR5K_EEPROM_MAX_CTLSAR5K_EEPROM_MAX_CTLS 32 eeprom.h  
439
AR5K_EEPROM_N_PD_CURVESAR5K_EEPROM_N_PD_CURVES 4 eeprom.h  
440
AR5K_EEPROM_N_XPD0_POINTSAR5K_EEPROM_N_XPD0_POINTS 4 eeprom.h  
441
AR5K_EEPROM_N_XPD3_POINTSAR5K_EEPROM_N_XPD3_POINTS 3 eeprom.h  
442
AR5K_EEPROM_N_PD_GAINSAR5K_EEPROM_N_PD_GAINS 4 eeprom.h  
443
AR5K_EEPROM_N_PD_POINTSAR5K_EEPROM_N_PD_POINTS 5 eeprom.h  
444
AR5K_EEPROM_N_INTERCEPT_10_2GHZAR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 eeprom.h  
445
AR5K_EEPROM_N_INTERCEPT_10_5GHZAR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 eeprom.h  
446
AR5K_EEPROM_POWER_MAR5K_EEPROM_POWER_M 0x3f eeprom.h  
447
AR5K_EEPROM_POWER_MINAR5K_EEPROM_POWER_MIN 0 eeprom.h  
448
AR5K_EEPROM_POWER_MAXAR5K_EEPROM_POWER_MAX 3150 eeprom.h  
449
AR5K_EEPROM_POWER_STEPAR5K_EEPROM_POWER_STEP 50 eeprom.h  
450
AR5K_EEPROM_POWER_TABLE_SIZEAR5K_EEPROM_POWER_TABLE_SIZE 64 eeprom.h  
451
AR5K_EEPROM_N_POWER_LOC_11BAR5K_EEPROM_N_POWER_LOC_11B 4 eeprom.h  
452
AR5K_EEPROM_N_POWER_LOC_11GAR5K_EEPROM_N_POWER_LOC_11G 6 eeprom.h  
453
AR5K_EEPROM_I_GAINAR5K_EEPROM_I_GAIN 10 eeprom.h  
454
AR5K_EEPROM_CCK_OFDM_DELTAAR5K_EEPROM_CCK_OFDM_DELTA 15 eeprom.h  
455
AR5K_EEPROM_N_IQ_CALAR5K_EEPROM_N_IQ_CAL 2 eeprom.h  
456
AR5K_CTL_FCCAR5K_CTL_FCC 0x10 eeprom.h  
457
AR5K_CTL_CUSTOMAR5K_CTL_CUSTOM 0x20 eeprom.h  
458
AR5K_CTL_ETSIAR5K_CTL_ETSI 0x30 eeprom.h  
459
AR5K_CTL_MKKAR5K_CTL_MKK 0x40 eeprom.h  
460
AR5K_CTL_NO_REGDOMAINAR5K_CTL_NO_REGDOMAIN 0xf0 eeprom.h  
461
AR5K_CTL_NO_CTLAR5K_CTL_NO_CTL 0xff eeprom.h  
462
AR5K_NOQCU_TXDP0AR5K_NOQCU_TXDP0 0x0000 reg.h Queue 0 - data
463
AR5K_NOQCU_TXDP1AR5K_NOQCU_TXDP1 0x0004 reg.h Queue 1 - beacons
464
AR5K_CRAR5K_CR 0x0008 reg.h Register Address
465
AR5K_CR_TXE0AR5K_CR_TXE0 0x00000001 reg.h TX Enable for queue 0 on 5210
466
AR5K_CR_TXE1AR5K_CR_TXE1 0x00000002 reg.h TX Enable for queue 1 on 5210
467
AR5K_CR_RXEAR5K_CR_RXE 0x00000004 reg.h RX Enable
468
AR5K_CR_TXD0AR5K_CR_TXD0 0x00000008 reg.h TX Disable for queue 0 on 5210
469
AR5K_CR_TXD1AR5K_CR_TXD1 0x00000010 reg.h TX Disable for queue 1 on 5210
470
AR5K_CR_RXDAR5K_CR_RXD 0x00000020 reg.h RX Disable
471
AR5K_CR_SWIAR5K_CR_SWI 0x00000040 reg.h Software Interrupt
472
AR5K_RXDPAR5K_RXDP 0x000c reg.h  
473
AR5K_CFGAR5K_CFG 0x0014 reg.h Register Address
474
AR5K_CFG_SWTDAR5K_CFG_SWTD 0x00000001 reg.h Byte-swap TX descriptor (for big endian archs)
475
AR5K_CFG_SWTBAR5K_CFG_SWTB 0x00000002 reg.h Byte-swap TX buffer
476
AR5K_CFG_SWRDAR5K_CFG_SWRD 0x00000004 reg.h Byte-swap RX descriptor
477
AR5K_CFG_SWRBAR5K_CFG_SWRB 0x00000008 reg.h Byte-swap RX buffer
478
AR5K_CFG_SWRGAR5K_CFG_SWRG 0x00000010 reg.h Byte-swap Register access
479
AR5K_CFG_IBSSAR5K_CFG_IBSS 0x00000020 reg.h 0-BSS, 1-IBSS [5211+]
480
AR5K_CFG_PHY_OKAR5K_CFG_PHY_OK 0x00000100 reg.h [5211+]
481
AR5K_CFG_EEBSAR5K_CFG_EEBS 0x00000200 reg.h EEPROM is busy
482
AR5K_CFG_CLKGDAR5K_CFG_CLKGD 0x00000400 reg.h Clock gated (Disable dynamic clock)
483
AR5K_CFG_TXCNTAR5K_CFG_TXCNT 0x00007800 reg.h Tx frame count (?) [5210]
484
AR5K_CFG_TXCNT_SAR5K_CFG_TXCNT_S 11 reg.h  
485
AR5K_CFG_TXFSTATAR5K_CFG_TXFSTAT 0x00008000 reg.h Tx frame status (?) [5210]
486
AR5K_CFG_TXFSTRTAR5K_CFG_TXFSTRT 0x00010000 reg.h [5210]
487
AR5K_CFG_PCI_THRESAR5K_CFG_PCI_THRES 0x00060000 reg.h PCI Master req q threshold [5211+]
488
AR5K_CFG_PCI_THRES_SAR5K_CFG_PCI_THRES_S 17 reg.h  
489
AR5K_IERAR5K_IER 0x0024 reg.h Register Address
490
AR5K_IER_DISABLEAR5K_IER_DISABLE 0x00000000 reg.h Disable card interrupts
491
AR5K_IER_ENABLEAR5K_IER_ENABLE 0x00000001 reg.h Enable card interrupts
492
AR5K_BCRAR5K_BCR 0x0028 reg.h Register Address
493
AR5K_BCR_APAR5K_BCR_AP 0x00000000 reg.h AP mode
494
AR5K_BCR_ADHOCAR5K_BCR_ADHOC 0x00000001 reg.h Ad-Hoc mode
495
AR5K_BCR_BDMAEAR5K_BCR_BDMAE 0x00000002 reg.h DMA enable
496
AR5K_BCR_TQ1FVAR5K_BCR_TQ1FV 0x00000004 reg.h Use Queue1 for CAB traffic
497
AR5K_BCR_TQ1VAR5K_BCR_TQ1V 0x00000008 reg.h Use Queue1 for Beacon traffic
498
AR5K_BCR_BCGETAR5K_BCR_BCGET 0x00000010 reg.h  
499
AR5K_RTSD0AR5K_RTSD0 0x0028 reg.h Register Address
500
AR5K_RTSD0_6AR5K_RTSD0_6 0x000000ff reg.h 6Mb RTS duration mask (?)
501
AR5K_RTSD0_6_SAR5K_RTSD0_6_S 0 reg.h 6Mb RTS duration shift (?)
502
AR5K_RTSD0_9AR5K_RTSD0_9 0x0000ff00 reg.h 9Mb
503
AR5K_RTSD0_9_SAR5K_RTSD0_9_S 8 reg.h  
504
AR5K_RTSD0_12AR5K_RTSD0_12 0x00ff0000 reg.h 12Mb
505
AR5K_RTSD0_12_SAR5K_RTSD0_12_S 16 reg.h  
506
AR5K_RTSD0_18AR5K_RTSD0_18 0xff000000 reg.h 16Mb
507
AR5K_RTSD0_18_SAR5K_RTSD0_18_S 24 reg.h  
508
AR5K_BSRAR5K_BSR 0x002c reg.h Register Address
509
AR5K_BSR_BDLYSWAR5K_BSR_BDLYSW 0x00000001 reg.h SW Beacon delay (?)
510
AR5K_BSR_BDLYDMAAR5K_BSR_BDLYDMA 0x00000002 reg.h DMA Beacon delay (?)
511
AR5K_BSR_TXQ1FAR5K_BSR_TXQ1F 0x00000004 reg.h Beacon queue (1) finished
512
AR5K_BSR_ATIMDLYAR5K_BSR_ATIMDLY 0x00000008 reg.h ATIM delay (?)
513
AR5K_BSR_SNPADHOCAR5K_BSR_SNPADHOC 0x00000100 reg.h Ad-hoc mode set (?)
514
AR5K_BSR_SNPBDMAEAR5K_BSR_SNPBDMAE 0x00000200 reg.h Beacon DMA enabled (?)
515
AR5K_BSR_SNPTQ1FVAR5K_BSR_SNPTQ1FV 0x00000400 reg.h Queue1 is used for CAB traffic (?)
516
AR5K_BSR_SNPTQ1VAR5K_BSR_SNPTQ1V 0x00000800 reg.h Queue1 is used for Beacon traffic (?)
517
AR5K_BSR_SNAPSHOTSVALIDAR5K_BSR_SNAPSHOTSVALID 0x00001000 reg.h BCR snapshots are valid (?)
518
AR5K_BSR_SWBA_CNTAR5K_BSR_SWBA_CNT 0x00ff0000 reg.h  
519
AR5K_RTSD1AR5K_RTSD1 0x002c reg.h Register Address
520
AR5K_RTSD1_24AR5K_RTSD1_24 0x000000ff reg.h 24Mb
521
AR5K_RTSD1_24_SAR5K_RTSD1_24_S 0 reg.h  
522
AR5K_RTSD1_36AR5K_RTSD1_36 0x0000ff00 reg.h 36Mb
523
AR5K_RTSD1_36_SAR5K_RTSD1_36_S 8 reg.h  
524
AR5K_RTSD1_48AR5K_RTSD1_48 0x00ff0000 reg.h 48Mb
525
AR5K_RTSD1_48_SAR5K_RTSD1_48_S 16 reg.h  
526
AR5K_RTSD1_54AR5K_RTSD1_54 0xff000000 reg.h 54Mb
527
AR5K_RTSD1_54_SAR5K_RTSD1_54_S 24 reg.h  
528
AR5K_TXCFGAR5K_TXCFG 0x0030 reg.h Register Address
529
AR5K_TXCFG_SDMAMRAR5K_TXCFG_SDMAMR 0x00000007 reg.h DMA size (read)
530
AR5K_TXCFG_SDMAMR_SAR5K_TXCFG_SDMAMR_S 0 reg.h  
531
AR5K_TXCFG_B_MODEAR5K_TXCFG_B_MODE 0x00000008 reg.h Set b mode for 5111 (enable 2111)
532
AR5K_TXCFG_TXFSTPAR5K_TXCFG_TXFSTP 0x00000008 reg.h TX DMA full Stop [5210]
533
AR5K_TXCFG_TXFULLAR5K_TXCFG_TXFULL 0x000003f0 reg.h TX Triger level mask
534
AR5K_TXCFG_TXFULL_SAR5K_TXCFG_TXFULL_S 4 reg.h  
535
AR5K_TXCFG_TXFULL_0BAR5K_TXCFG_TXFULL_0B 0x00000000 reg.h  
536
AR5K_TXCFG_TXFULL_64BAR5K_TXCFG_TXFULL_64B 0x00000010 reg.h  
537
AR5K_TXCFG_TXFULL_128BAR5K_TXCFG_TXFULL_128B 0x00000020 reg.h  
538
AR5K_TXCFG_TXFULL_192BAR5K_TXCFG_TXFULL_192B 0x00000030 reg.h  
539
AR5K_TXCFG_TXFULL_256BAR5K_TXCFG_TXFULL_256B 0x00000040 reg.h  
540
AR5K_TXCFG_TXCONT_ENAR5K_TXCFG_TXCONT_EN 0x00000080 reg.h  
541
AR5K_TXCFG_DMASIZEAR5K_TXCFG_DMASIZE 0x00000100 reg.h Flag for passing DMA size [5210]
542
AR5K_TXCFG_JUMBO_DESC_ENAR5K_TXCFG_JUMBO_DESC_EN 0x00000400 reg.h Enable jumbo tx descriptors [5211+]
543
AR5K_TXCFG_ADHOC_BCN_ATIMAR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 reg.h Adhoc Beacon ATIM Policy
544
AR5K_TXCFG_ATIM_WINDOW_DEF_DISAR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 reg.h Disable ATIM window defer [5211+]
545
AR5K_TXCFG_RTSRNDAR5K_TXCFG_RTSRND 0x00001000 reg.h [5211+]
546
AR5K_TXCFG_FRMPAD_DISAR5K_TXCFG_FRMPAD_DIS 0x00002000 reg.h [5211+]
547
AR5K_TXCFG_RDY_CBR_DISAR5K_TXCFG_RDY_CBR_DIS 0x00004000 reg.h Ready time CBR disable [5211+]
548
AR5K_TXCFG_JUMBO_FRM_MODEAR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 reg.h Jumbo frame mode [5211+]
549
AR5K_TXCFG_DCU_DBL_BUF_DISAR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 reg.h Disable double buffering on DCU
550
AR5K_TXCFG_DCU_CACHING_DISAR5K_TXCFG_DCU_CACHING_DIS 0x00010000 reg.h Disable DCU caching
551
AR5K_RXCFGAR5K_RXCFG 0x0034 reg.h Register Address
552
AR5K_RXCFG_SDMAMWAR5K_RXCFG_SDMAMW 0x00000007 reg.h DMA size (write)
553
AR5K_RXCFG_SDMAMW_SAR5K_RXCFG_SDMAMW_S 0 reg.h  
554
AR5K_RXCFG_ZLFDMAAR5K_RXCFG_ZLFDMA 0x00000008 reg.h Enable Zero-length frame DMA
555
AR5K_RXCFG_DEF_ANTENNAAR5K_RXCFG_DEF_ANTENNA 0x00000010 reg.h Default antenna (?)
556
AR5K_RXCFG_JUMBO_RXEAR5K_RXCFG_JUMBO_RXE 0x00000020 reg.h Enable jumbo rx descriptors [5211+]
557
AR5K_RXCFG_JUMBO_WRAPAR5K_RXCFG_JUMBO_WRAP 0x00000040 reg.h Wrap jumbo frames [5211+]
558
AR5K_RXCFG_SLE_ENTRYAR5K_RXCFG_SLE_ENTRY 0x00000080 reg.h Sleep entry policy
559
AR5K_RXJLAAR5K_RXJLA 0x0038 reg.h  
560
AR5K_MIBCAR5K_MIBC 0x0040 reg.h Register Address
561
AR5K_MIBC_COWAR5K_MIBC_COW 0x00000001 reg.h Warn test indicator
562
AR5K_MIBC_FMCAR5K_MIBC_FMC 0x00000002 reg.h Freeze MIB Counters
563
AR5K_MIBC_CMCAR5K_MIBC_CMC 0x00000004 reg.h Clean MIB Counters
564
AR5K_MIBC_MCSAR5K_MIBC_MCS 0x00000008 reg.h MIB counter strobe
565
AR5K_TOPSAR5K_TOPS 0x0044 reg.h  
566
AR5K_TOPS_MAR5K_TOPS_M 0x0000ffff reg.h  
567
AR5K_RXNOFRMAR5K_RXNOFRM 0x0048 reg.h  
568
AR5K_RXNOFRM_MAR5K_RXNOFRM_M 0x000003ff reg.h  
569
AR5K_TXNOFRMAR5K_TXNOFRM 0x004c reg.h  
570
AR5K_TXNOFRM_MAR5K_TXNOFRM_M 0x000003ff reg.h  
571
AR5K_TXNOFRM_QCUAR5K_TXNOFRM_QCU 0x000ffc00 reg.h  
572
AR5K_TXNOFRM_QCU_SAR5K_TXNOFRM_QCU_S 10 reg.h  
573
AR5K_RPGTOAR5K_RPGTO 0x0050 reg.h  
574
AR5K_RPGTO_MAR5K_RPGTO_M 0x000003ff reg.h  
575
AR5K_RFCNTAR5K_RFCNT 0x0054 reg.h  
576
AR5K_RFCNT_MAR5K_RFCNT_M 0x0000001f reg.h [5211+] (?)
577
AR5K_RFCNT_RFCLAR5K_RFCNT_RFCL 0x0000000f reg.h [5210]
578
AR5K_MISCAR5K_MISC 0x0058 reg.h Register Address
579
AR5K_MISC_DMA_OBS_MAR5K_MISC_DMA_OBS_M 0x000001e0 reg.h  
580
AR5K_MISC_DMA_OBS_SAR5K_MISC_DMA_OBS_S 5 reg.h  
581
AR5K_MISC_MISC_OBS_MAR5K_MISC_MISC_OBS_M 0x00000e00 reg.h  
582
AR5K_MISC_MISC_OBS_SAR5K_MISC_MISC_OBS_S 9 reg.h  
583
AR5K_MISC_MAC_OBS_LSB_MAR5K_MISC_MAC_OBS_LSB_M 0x00007000 reg.h  
584
AR5K_MISC_MAC_OBS_LSB_SAR5K_MISC_MAC_OBS_LSB_S 12 reg.h  
585
AR5K_MISC_MAC_OBS_MSB_MAR5K_MISC_MAC_OBS_MSB_M 0x00038000 reg.h  
586
AR5K_MISC_MAC_OBS_MSB_SAR5K_MISC_MAC_OBS_MSB_S 15 reg.h  
587
AR5K_MISC_LED_DECAYAR5K_MISC_LED_DECAY 0x001c0000 reg.h [5210]
588
AR5K_MISC_LED_BLINKAR5K_MISC_LED_BLINK 0x00e00000 reg.h [5210]
589
AR5K_QCUDCU_CLKGTAR5K_QCUDCU_CLKGT 0x005c reg.h Register Address (?)
590
AR5K_QCUDCU_CLKGT_QCUAR5K_QCUDCU_CLKGT_QCU 0x0000ffff reg.h Mask for QCU clock
591
AR5K_QCUDCU_CLKGT_DCUAR5K_QCUDCU_CLKGT_DCU 0x07ff0000 reg.h Mask for DCU clock
592
AR5K_ISRAR5K_ISR 0x001c reg.h Register Address [5210]
593
AR5K_PISRAR5K_PISR 0x0080 reg.h Register Address [5211+]
594
AR5K_ISR_RXOKAR5K_ISR_RXOK 0x00000001 reg.h Frame successfuly recieved
595
AR5K_ISR_RXDESCAR5K_ISR_RXDESC 0x00000002 reg.h RX descriptor request
596
AR5K_ISR_RXERRAR5K_ISR_RXERR 0x00000004 reg.h Receive error
597
AR5K_ISR_RXNOFRMAR5K_ISR_RXNOFRM 0x00000008 reg.h No frame received (receive timeout)
598
AR5K_ISR_RXEOLAR5K_ISR_RXEOL 0x00000010 reg.h Empty RX descriptor
599
AR5K_ISR_RXORNAR5K_ISR_RXORN 0x00000020 reg.h Receive FIFO overrun
600
AR5K_ISR_TXOKAR5K_ISR_TXOK 0x00000040 reg.h Frame successfuly transmited
601
AR5K_ISR_TXDESCAR5K_ISR_TXDESC 0x00000080 reg.h TX descriptor request
602
AR5K_ISR_TXERRAR5K_ISR_TXERR 0x00000100 reg.h Transmit error
603
AR5K_ISR_TXNOFRMAR5K_ISR_TXNOFRM 0x00000200 reg.h No frame transmited (transmit timeout)
604
AR5K_ISR_TXEOLAR5K_ISR_TXEOL 0x00000400 reg.h Empty TX descriptor
605
AR5K_ISR_TXURNAR5K_ISR_TXURN 0x00000800 reg.h Transmit FIFO underrun
606
AR5K_ISR_MIBAR5K_ISR_MIB 0x00001000 reg.h Update MIB counters
607
AR5K_ISR_SWIAR5K_ISR_SWI 0x00002000 reg.h Software interrupt
608
AR5K_ISR_RXPHYAR5K_ISR_RXPHY 0x00004000 reg.h PHY error
609
AR5K_ISR_RXKCMAR5K_ISR_RXKCM 0x00008000 reg.h RX Key cache miss
610
AR5K_ISR_SWBAAR5K_ISR_SWBA 0x00010000 reg.h Software beacon alert
611
AR5K_ISR_BRSSIAR5K_ISR_BRSSI 0x00020000 reg.h Beacon rssi below threshold (?)
612
AR5K_ISR_BMISSAR5K_ISR_BMISS 0x00040000 reg.h Beacon missed
613
AR5K_ISR_HIUERRAR5K_ISR_HIUERR 0x00080000 reg.h Host Interface Unit error [5211+]
614
AR5K_ISR_BNRAR5K_ISR_BNR 0x00100000 reg.h Beacon not ready [5211+]
615
AR5K_ISR_MCABTAR5K_ISR_MCABT 0x00100000 reg.h Master Cycle Abort [5210]
616
AR5K_ISR_RXCHIRPAR5K_ISR_RXCHIRP 0x00200000 reg.h CHIRP Received [5212+]
617
AR5K_ISR_SSERRAR5K_ISR_SSERR 0x00200000 reg.h Signaled System Error [5210]
618
AR5K_ISR_DPERRAR5K_ISR_DPERR 0x00400000 reg.h Det par Error (?) [5210]
619
AR5K_ISR_RXDOPPLERAR5K_ISR_RXDOPPLER 0x00400000 reg.h Doppler chirp received [5212+]
620
AR5K_ISR_TIMAR5K_ISR_TIM 0x00800000 reg.h [5211+]
621
AR5K_ISR_BCNMISCAR5K_ISR_BCNMISC 0x00800000 reg.h 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
622
AR5K_ISR_GPIOAR5K_ISR_GPIO 0x01000000 reg.h GPIO (rf kill)
623
AR5K_ISR_QCBRORNAR5K_ISR_QCBRORN 0x02000000 reg.h QCU CBR overrun [5211+]
624
AR5K_ISR_QCBRURNAR5K_ISR_QCBRURN 0x04000000 reg.h QCU CBR underrun [5211+]
625
AR5K_ISR_QTRIGAR5K_ISR_QTRIG 0x08000000 reg.h QCU scheduling trigger [5211+]
626
AR5K_SISR0AR5K_SISR0 0x0084 reg.h Register Address [5211+]
627
AR5K_SISR0_QCU_TXOKAR5K_SISR0_QCU_TXOK 0x000003ff reg.h Mask for QCU_TXOK
628
AR5K_SISR0_QCU_TXOK_SAR5K_SISR0_QCU_TXOK_S 0 reg.h  
629
AR5K_SISR0_QCU_TXDESCAR5K_SISR0_QCU_TXDESC 0x03ff0000 reg.h Mask for QCU_TXDESC
630
AR5K_SISR0_QCU_TXDESC_SAR5K_SISR0_QCU_TXDESC_S 16 reg.h  
631
AR5K_SISR1AR5K_SISR1 0x0088 reg.h Register Address [5211+]
632
AR5K_SISR1_QCU_TXERRAR5K_SISR1_QCU_TXERR 0x000003ff reg.h Mask for QCU_TXERR
633
AR5K_SISR1_QCU_TXERR_SAR5K_SISR1_QCU_TXERR_S 0 reg.h  
634
AR5K_SISR1_QCU_TXEOLAR5K_SISR1_QCU_TXEOL 0x03ff0000 reg.h Mask for QCU_TXEOL
635
AR5K_SISR1_QCU_TXEOL_SAR5K_SISR1_QCU_TXEOL_S 16 reg.h  
636
AR5K_SISR2AR5K_SISR2 0x008c reg.h Register Address [5211+]
637
AR5K_SISR2_QCU_TXURNAR5K_SISR2_QCU_TXURN 0x000003ff reg.h Mask for QCU_TXURN
638
AR5K_SISR2_QCU_TXURN_SAR5K_SISR2_QCU_TXURN_S 0 reg.h  
639
AR5K_SISR2_MCABTAR5K_SISR2_MCABT 0x00100000 reg.h Master Cycle Abort
640
AR5K_SISR2_SSERRAR5K_SISR2_SSERR 0x00200000 reg.h Signaled System Error
641
AR5K_SISR2_DPERRAR5K_SISR2_DPERR 0x00400000 reg.h Bus parity error
642
AR5K_SISR2_TIMAR5K_SISR2_TIM 0x01000000 reg.h [5212+]
643
AR5K_SISR2_CAB_ENDAR5K_SISR2_CAB_END 0x02000000 reg.h [5212+]
644
AR5K_SISR2_DTIM_SYNCAR5K_SISR2_DTIM_SYNC 0x04000000 reg.h DTIM sync lost [5212+]
645
AR5K_SISR2_BCN_TIMEOUTAR5K_SISR2_BCN_TIMEOUT 0x08000000 reg.h Beacon Timeout [5212+]
646
AR5K_SISR2_CAB_TIMEOUTAR5K_SISR2_CAB_TIMEOUT 0x10000000 reg.h CAB Timeout [5212+]
647
AR5K_SISR2_DTIMAR5K_SISR2_DTIM 0x20000000 reg.h [5212+]
648
AR5K_SISR2_TSFOORAR5K_SISR2_TSFOOR 0x80000000 reg.h TSF OOR (?)
649
AR5K_SISR3AR5K_SISR3 0x0090 reg.h Register Address [5211+]
650
AR5K_SISR3_QCBRORNAR5K_SISR3_QCBRORN 0x000003ff reg.h Mask for QCBRORN
651
AR5K_SISR3_QCBRORN_SAR5K_SISR3_QCBRORN_S 0 reg.h  
652
AR5K_SISR3_QCBRURNAR5K_SISR3_QCBRURN 0x03ff0000 reg.h Mask for QCBRURN
653
AR5K_SISR3_QCBRURN_SAR5K_SISR3_QCBRURN_S 16 reg.h  
654
AR5K_SISR4AR5K_SISR4 0x0094 reg.h Register Address [5211+]
655
AR5K_SISR4_QTRIGAR5K_SISR4_QTRIG 0x000003ff reg.h Mask for QTRIG
656
AR5K_SISR4_QTRIG_SAR5K_SISR4_QTRIG_S 0 reg.h  
657
AR5K_RAC_PISRAR5K_RAC_PISR 0x00c0 reg.h Read and clear PISR
658
AR5K_RAC_SISR0AR5K_RAC_SISR0 0x00c4 reg.h Read and clear SISR0
659
AR5K_RAC_SISR1AR5K_RAC_SISR1 0x00c8 reg.h Read and clear SISR1
660
AR5K_RAC_SISR2AR5K_RAC_SISR2 0x00cc reg.h Read and clear SISR2
661
AR5K_RAC_SISR3AR5K_RAC_SISR3 0x00d0 reg.h Read and clear SISR3
662
AR5K_RAC_SISR4AR5K_RAC_SISR4 0x00d4 reg.h Read and clear SISR4
663
AR5K_IMRAR5K_IMR 0x0020 reg.h Register Address [5210]
664
AR5K_PIMRAR5K_PIMR 0x00a0 reg.h Register Address [5211+]
665
AR5K_IMR_RXOKAR5K_IMR_RXOK 0x00000001 reg.h Frame successfuly recieved
666
AR5K_IMR_RXDESCAR5K_IMR_RXDESC 0x00000002 reg.h RX descriptor request
667
AR5K_IMR_RXERRAR5K_IMR_RXERR 0x00000004 reg.h Receive error
668
AR5K_IMR_RXNOFRMAR5K_IMR_RXNOFRM 0x00000008 reg.h No frame received (receive timeout)
669
AR5K_IMR_RXEOLAR5K_IMR_RXEOL 0x00000010 reg.h Empty RX descriptor
670
AR5K_IMR_RXORNAR5K_IMR_RXORN 0x00000020 reg.h Receive FIFO overrun
671
AR5K_IMR_TXOKAR5K_IMR_TXOK 0x00000040 reg.h Frame successfuly transmited
672
AR5K_IMR_TXDESCAR5K_IMR_TXDESC 0x00000080 reg.h TX descriptor request
673
AR5K_IMR_TXERRAR5K_IMR_TXERR 0x00000100 reg.h Transmit error
674
AR5K_IMR_TXNOFRMAR5K_IMR_TXNOFRM 0x00000200 reg.h No frame transmited (transmit timeout)
675
AR5K_IMR_TXEOLAR5K_IMR_TXEOL 0x00000400 reg.h Empty TX descriptor
676
AR5K_IMR_TXURNAR5K_IMR_TXURN 0x00000800 reg.h Transmit FIFO underrun
677
AR5K_IMR_MIBAR5K_IMR_MIB 0x00001000 reg.h Update MIB counters
678
AR5K_IMR_SWIAR5K_IMR_SWI 0x00002000 reg.h Software interrupt
679
AR5K_IMR_RXPHYAR5K_IMR_RXPHY 0x00004000 reg.h PHY error
680
AR5K_IMR_RXKCMAR5K_IMR_RXKCM 0x00008000 reg.h RX Key cache miss
681
AR5K_IMR_SWBAAR5K_IMR_SWBA 0x00010000 reg.h Software beacon alert
682
AR5K_IMR_BRSSIAR5K_IMR_BRSSI 0x00020000 reg.h Beacon rssi below threshold (?)
683
AR5K_IMR_BMISSAR5K_IMR_BMISS 0x00040000 reg.h Beacon missed
684
AR5K_IMR_HIUERRAR5K_IMR_HIUERR 0x00080000 reg.h Host Interface Unit error [5211+]
685
AR5K_IMR_BNRAR5K_IMR_BNR 0x00100000 reg.h Beacon not ready [5211+]
686
AR5K_IMR_MCABTAR5K_IMR_MCABT 0x00100000 reg.h Master Cycle Abort [5210]
687
AR5K_IMR_RXCHIRPAR5K_IMR_RXCHIRP 0x00200000 reg.h CHIRP Received [5212+]
688
AR5K_IMR_SSERRAR5K_IMR_SSERR 0x00200000 reg.h Signaled System Error [5210]
689
AR5K_IMR_DPERRAR5K_IMR_DPERR 0x00400000 reg.h Det par Error (?) [5210]
690
AR5K_IMR_RXDOPPLERAR5K_IMR_RXDOPPLER 0x00400000 reg.h Doppler chirp received [5212+]
691
AR5K_IMR_TIMAR5K_IMR_TIM 0x00800000 reg.h [5211+]
692
AR5K_IMR_BCNMISCAR5K_IMR_BCNMISC 0x00800000 reg.h 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
693
AR5K_IMR_GPIOAR5K_IMR_GPIO 0x01000000 reg.h GPIO (rf kill)
694
AR5K_IMR_QCBRORNAR5K_IMR_QCBRORN 0x02000000 reg.h QCU CBR overrun (?) [5211+]
695
AR5K_IMR_QCBRURNAR5K_IMR_QCBRURN 0x04000000 reg.h QCU CBR underrun (?) [5211+]
696
AR5K_IMR_QTRIGAR5K_IMR_QTRIG 0x08000000 reg.h QCU scheduling trigger [5211+]
697
AR5K_SIMR0AR5K_SIMR0 0x00a4 reg.h Register Address [5211+]
698
AR5K_SIMR0_QCU_TXOKAR5K_SIMR0_QCU_TXOK 0x000003ff reg.h Mask for QCU_TXOK
699
AR5K_SIMR0_QCU_TXOK_SAR5K_SIMR0_QCU_TXOK_S 0 reg.h  
700
AR5K_SIMR0_QCU_TXDESCAR5K_SIMR0_QCU_TXDESC 0x03ff0000 reg.h Mask for QCU_TXDESC
701
AR5K_SIMR0_QCU_TXDESC_SAR5K_SIMR0_QCU_TXDESC_S 16 reg.h  
702
AR5K_SIMR1AR5K_SIMR1 0x00a8 reg.h Register Address [5211+]
703
AR5K_SIMR1_QCU_TXERRAR5K_SIMR1_QCU_TXERR 0x000003ff reg.h Mask for QCU_TXERR
704
AR5K_SIMR1_QCU_TXERR_SAR5K_SIMR1_QCU_TXERR_S 0 reg.h  
705
AR5K_SIMR1_QCU_TXEOLAR5K_SIMR1_QCU_TXEOL 0x03ff0000 reg.h Mask for QCU_TXEOL
706
AR5K_SIMR1_QCU_TXEOL_SAR5K_SIMR1_QCU_TXEOL_S 16 reg.h  
707
AR5K_SIMR2AR5K_SIMR2 0x00ac reg.h Register Address [5211+]
708
AR5K_SIMR2_QCU_TXURNAR5K_SIMR2_QCU_TXURN 0x000003ff reg.h Mask for QCU_TXURN
709
AR5K_SIMR2_QCU_TXURN_SAR5K_SIMR2_QCU_TXURN_S 0 reg.h  
710
AR5K_SIMR2_MCABTAR5K_SIMR2_MCABT 0x00100000 reg.h Master Cycle Abort
711
AR5K_SIMR2_SSERRAR5K_SIMR2_SSERR 0x00200000 reg.h Signaled System Error
712
AR5K_SIMR2_DPERRAR5K_SIMR2_DPERR 0x00400000 reg.h Bus parity error
713
AR5K_SIMR2_TIMAR5K_SIMR2_TIM 0x01000000 reg.h [5212+]
714
AR5K_SIMR2_CAB_ENDAR5K_SIMR2_CAB_END 0x02000000 reg.h [5212+]
715
AR5K_SIMR2_DTIM_SYNCAR5K_SIMR2_DTIM_SYNC 0x04000000 reg.h DTIM Sync lost [5212+]
716
AR5K_SIMR2_BCN_TIMEOUTAR5K_SIMR2_BCN_TIMEOUT 0x08000000 reg.h Beacon Timeout [5212+]
717
AR5K_SIMR2_CAB_TIMEOUTAR5K_SIMR2_CAB_TIMEOUT 0x10000000 reg.h CAB Timeout [5212+]
718
AR5K_SIMR2_DTIMAR5K_SIMR2_DTIM 0x20000000 reg.h [5212+]
719
AR5K_SIMR2_TSFOORAR5K_SIMR2_TSFOOR 0x80000000 reg.h TSF OOR (?)
720
AR5K_SIMR3AR5K_SIMR3 0x00b0 reg.h Register Address [5211+]
721
AR5K_SIMR3_QCBRORNAR5K_SIMR3_QCBRORN 0x000003ff reg.h Mask for QCBRORN
722
AR5K_SIMR3_QCBRORN_SAR5K_SIMR3_QCBRORN_S 0 reg.h  
723
AR5K_SIMR3_QCBRURNAR5K_SIMR3_QCBRURN 0x03ff0000 reg.h Mask for QCBRURN
724
AR5K_SIMR3_QCBRURN_SAR5K_SIMR3_QCBRURN_S 16 reg.h  
725
AR5K_SIMR4AR5K_SIMR4 0x00b4 reg.h Register Address [5211+]
726
AR5K_SIMR4_QTRIGAR5K_SIMR4_QTRIG 0x000003ff reg.h Mask for QTRIG
727
AR5K_SIMR4_QTRIG_SAR5K_SIMR4_QTRIG_S 0 reg.h  
728
AR5K_DCM_ADDRAR5K_DCM_ADDR 0x0400 reg.h Decompression mask address (index)
729
AR5K_DCM_DATAAR5K_DCM_DATA 0x0404 reg.h Decompression mask data
730
AR5K_WOW_PCFGAR5K_WOW_PCFG 0x0410 reg.h Register Address
731
AR5K_WOW_PCFG_PAT_MATCH_ENAR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 reg.h Pattern match enable
732
AR5K_WOW_PCFG_LONG_FRAME_POLAR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 reg.h Long frame policy
733
AR5K_WOW_PCFG_WOBMISSAR5K_WOW_PCFG_WOBMISS 0x00000004 reg.h Wake on bea(con) miss (?)
734
AR5K_WOW_PCFG_PAT_0_ENAR5K_WOW_PCFG_PAT_0_EN 0x00000100 reg.h Enable pattern 0
735
AR5K_WOW_PCFG_PAT_1_ENAR5K_WOW_PCFG_PAT_1_EN 0x00000200 reg.h Enable pattern 1
736
AR5K_WOW_PCFG_PAT_2_ENAR5K_WOW_PCFG_PAT_2_EN 0x00000400 reg.h Enable pattern 2
737
AR5K_WOW_PCFG_PAT_3_ENAR5K_WOW_PCFG_PAT_3_EN 0x00000800 reg.h Enable pattern 3
738
AR5K_WOW_PCFG_PAT_4_ENAR5K_WOW_PCFG_PAT_4_EN 0x00001000 reg.h Enable pattern 4
739
AR5K_WOW_PCFG_PAT_5_ENAR5K_WOW_PCFG_PAT_5_EN 0x00002000 reg.h Enable pattern 5
740
AR5K_WOW_PAT_IDXAR5K_WOW_PAT_IDX 0x0414 reg.h  
741
AR5K_WOW_PAT_DATAAR5K_WOW_PAT_DATA 0x0418 reg.h Register Address
742
AR5K_WOW_PAT_DATA_0_3_VAR5K_WOW_PAT_DATA_0_3_V 0x00000001 reg.h Pattern 0, 3 value
743
AR5K_WOW_PAT_DATA_1_4_VAR5K_WOW_PAT_DATA_1_4_V 0x00000100 reg.h Pattern 1, 4 value
744
AR5K_WOW_PAT_DATA_2_5_VAR5K_WOW_PAT_DATA_2_5_V 0x00010000 reg.h Pattern 2, 5 value
745
AR5K_WOW_PAT_DATA_0_3_MAR5K_WOW_PAT_DATA_0_3_M 0x01000000 reg.h Pattern 0, 3 mask
746
AR5K_WOW_PAT_DATA_1_4_MAR5K_WOW_PAT_DATA_1_4_M 0x04000000 reg.h Pattern 1, 4 mask
747
AR5K_WOW_PAT_DATA_2_5_MAR5K_WOW_PAT_DATA_2_5_M 0x10000000 reg.h Pattern 2, 5 mask
748
AR5K_DCCFGAR5K_DCCFG 0x0420 reg.h Register Address
749
AR5K_DCCFG_GLOBAL_ENAR5K_DCCFG_GLOBAL_EN 0x00000001 reg.h Enable decompression on all queues
750
AR5K_DCCFG_BYPASS_ENAR5K_DCCFG_BYPASS_EN 0x00000002 reg.h Bypass decompression
751
AR5K_DCCFG_BCAST_ENAR5K_DCCFG_BCAST_EN 0x00000004 reg.h Enable decompression for bcast frames
752
AR5K_DCCFG_MCAST_ENAR5K_DCCFG_MCAST_EN 0x00000008 reg.h Enable decompression for mcast frames
753
AR5K_CCFGAR5K_CCFG 0x0600 reg.h Register Address
754
AR5K_CCFG_WINDOW_SIZEAR5K_CCFG_WINDOW_SIZE 0x00000007 reg.h Compression window size
755
AR5K_CCFG_CPC_ENAR5K_CCFG_CPC_EN 0x00000008 reg.h Enable performance counters
756
AR5K_CCFG_CCUAR5K_CCFG_CCU 0x0604 reg.h Register Address
757
AR5K_CCFG_CCU_CUP_ENAR5K_CCFG_CCU_CUP_EN 0x00000001 reg.h CCU Catchup enable
758
AR5K_CCFG_CCU_CREDITAR5K_CCFG_CCU_CREDIT 0x00000002 reg.h CCU Credit (field)
759
AR5K_CCFG_CCU_CD_THRESAR5K_CCFG_CCU_CD_THRES 0x00000080 reg.h CCU Cyc(lic?) debt threshold (field)
760
AR5K_CCFG_CCU_CUP_LCNTAR5K_CCFG_CCU_CUP_LCNT 0x00010000 reg.h CCU Catchup lit(?) count
761
AR5K_CCFG_CCU_INITAR5K_CCFG_CCU_INIT 0x00100200 reg.h Initial value during reset
762
AR5K_CPC0AR5K_CPC0 0x0610 reg.h Compression performance counter 0
763
AR5K_CPC1AR5K_CPC1 0x0614 reg.h Compression performance counter 1
764
AR5K_CPC2AR5K_CPC2 0x0618 reg.h Compression performance counter 2
765
AR5K_CPC3AR5K_CPC3 0x061c reg.h Compression performance counter 3
766
AR5K_CPCOVFAR5K_CPCOVF 0x0620 reg.h Compression performance overflow
767
AR5K_QCU_TXDP_BASEAR5K_QCU_TXDP_BASE 0x0800 reg.h Register Address - Queue0 TXDP
768
AR5K_QCU_TXEAR5K_QCU_TXE 0x0840 reg.h  
769
AR5K_QCU_TXDAR5K_QCU_TXD 0x0880 reg.h  
770
AR5K_QCU_CBRCFG_BASEAR5K_QCU_CBRCFG_BASE 0x08c0 reg.h Register Address - Queue0 CBRCFG
771
AR5K_QCU_CBRCFG_INTVALAR5K_QCU_CBRCFG_INTVAL 0x00ffffff reg.h CBR Interval mask
772
AR5K_QCU_CBRCFG_INTVAL_SAR5K_QCU_CBRCFG_INTVAL_S 0 reg.h  
773
AR5K_QCU_CBRCFG_ORN_THRESAR5K_QCU_CBRCFG_ORN_THRES 0xff000000 reg.h CBR overrun threshold mask
774
AR5K_QCU_CBRCFG_ORN_THRES_SAR5K_QCU_CBRCFG_ORN_THRES_S 24 reg.h  
775
AR5K_QCU_RDYTIMECFG_BASEAR5K_QCU_RDYTIMECFG_BASE 0x0900 reg.h Register Address - Queue0 RDYTIMECFG
776
AR5K_QCU_RDYTIMECFG_INTVALAR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff reg.h Ready time interval mask
777
AR5K_QCU_RDYTIMECFG_INTVAL_SAR5K_QCU_RDYTIMECFG_INTVAL_S 0 reg.h  
778
AR5K_QCU_RDYTIMECFG_ENABLEAR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 reg.h Ready time enable mask
779
AR5K_QCU_ONESHOTARM_SETAR5K_QCU_ONESHOTARM_SET 0x0940 reg.h Register Address -QCU "one shot arm set (?)"
780
AR5K_QCU_ONESHOTARM_SET_MAR5K_QCU_ONESHOTARM_SET_M 0x0000ffff reg.h  
781
AR5K_QCU_ONESHOTARM_CLEARAR5K_QCU_ONESHOTARM_CLEAR 0x0980 reg.h Register Address -QCU "one shot arm clear (?)"
782
AR5K_QCU_ONESHOTARM_CLEAR_MAR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff reg.h  
783
AR5K_QCU_MISC_BASEAR5K_QCU_MISC_BASE 0x09c0 reg.h Register Address -Queue0 MISC
784
AR5K_QCU_MISC_FRSHED_MAR5K_QCU_MISC_FRSHED_M 0x0000000f reg.h Frame sheduling mask
785
AR5K_QCU_MISC_FRSHED_ASAPAR5K_QCU_MISC_FRSHED_ASAP 0 reg.h ASAP
786
AR5K_QCU_MISC_FRSHED_CBRAR5K_QCU_MISC_FRSHED_CBR 1 reg.h Constant Bit Rate
787
AR5K_QCU_MISC_FRSHED_DBA_GTAR5K_QCU_MISC_FRSHED_DBA_GT 2 reg.h DMA Beacon alert gated
788
AR5K_QCU_MISC_FRSHED_TIM_GTAR5K_QCU_MISC_FRSHED_TIM_GT 3 reg.h TIMT gated
789
AR5K_QCU_MISC_FRSHED_BCN_SENT_GAR5K_QCU_MISC_FRSHED_BCN_SENT_G 4 reg.h Beacon sent gated
790
AR5K_QCU_MISC_ONESHOT_ENABLEAR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 reg.h Oneshot enable
791
AR5K_QCU_MISC_CBREXP_DISAR5K_QCU_MISC_CBREXP_DIS 0x00000020 reg.h Disable CBR expired counter (normal queue)
792
AR5K_QCU_MISC_CBREXP_BCN_DISAR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 reg.h Disable CBR expired counter (beacon queue)
793
AR5K_QCU_MISC_BCN_ENABLEAR5K_QCU_MISC_BCN_ENABLE 0x00000080 reg.h Enable Beacon use
794
AR5K_QCU_MISC_CBR_THRES_ENABLEAR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 reg.h CBR expired threshold enabled
795
AR5K_QCU_MISC_RDY_VEOL_POLICYAR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 reg.h TXE reset when RDYTIME expired or VEOL
796
AR5K_QCU_MISC_CBR_RESET_CNTAR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 reg.h CBR threshold (counter) reset
797
AR5K_QCU_MISC_DCU_EARLYAR5K_QCU_MISC_DCU_EARLY 0x00000800 reg.h DCU early termination
798
AR5K_QCU_MISC_DCU_CMP_ENAR5K_QCU_MISC_DCU_CMP_EN 0x00001000 reg.h Enable frame compression
799
AR5K_QCU_STS_BASEAR5K_QCU_STS_BASE 0x0a00 reg.h Register Address - Queue0 STS
800
AR5K_QCU_STS_FRMPENDCNTAR5K_QCU_STS_FRMPENDCNT 0x00000003 reg.h Frames pending counter
801
AR5K_QCU_STS_CBREXPCNTAR5K_QCU_STS_CBREXPCNT 0x0000ff00 reg.h CBR expired counter
802
AR5K_QCU_RDYTIMESHDNAR5K_QCU_RDYTIMESHDN 0x0a40 reg.h  
803
AR5K_QCU_RDYTIMESHDN_MAR5K_QCU_RDYTIMESHDN_M 0x000003ff reg.h  
804
AR5K_QCU_CBB_SELECTAR5K_QCU_CBB_SELECT 0x0b00 reg.h  
805
AR5K_QCU_CBB_ADDRAR5K_QCU_CBB_ADDR 0x0b04 reg.h  
806
AR5K_QCU_CBB_ADDR_SAR5K_QCU_CBB_ADDR_S 9 reg.h  
807
AR5K_QCU_CBCFGAR5K_QCU_CBCFG 0x0b08 reg.h  
808
AR5K_DCU_QCUMASK_BASEAR5K_DCU_QCUMASK_BASE 0x1000 reg.h Register Address -Queue0 DCU_QCUMASK
809
AR5K_DCU_QCUMASK_MAR5K_DCU_QCUMASK_M 0x000003ff reg.h  
810
AR5K_DCU_LCL_IFS_BASEAR5K_DCU_LCL_IFS_BASE 0x1040 reg.h Register Address -Queue0 DCU_LCL_IFS
811
AR5K_DCU_LCL_IFS_CW_MINAR5K_DCU_LCL_IFS_CW_MIN 0x000003ff reg.h Minimum Contention Window
812
AR5K_DCU_LCL_IFS_CW_MIN_SAR5K_DCU_LCL_IFS_CW_MIN_S 0 reg.h  
813
AR5K_DCU_LCL_IFS_CW_MAXAR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 reg.h Maximum Contention Window
814
AR5K_DCU_LCL_IFS_CW_MAX_SAR5K_DCU_LCL_IFS_CW_MAX_S 10 reg.h  
815
AR5K_DCU_LCL_IFS_AIFSAR5K_DCU_LCL_IFS_AIFS 0x0ff00000 reg.h Arbitrated Interframe Space
816
AR5K_DCU_LCL_IFS_AIFS_SAR5K_DCU_LCL_IFS_AIFS_S 20 reg.h  
817
AR5K_DCU_LCL_IFS_AIFS_MAXAR5K_DCU_LCL_IFS_AIFS_MAX 0xfc reg.h Anything above that can cause DCU to hang
818
AR5K_DCU_RETRY_LMT_BASEAR5K_DCU_RETRY_LMT_BASE 0x1080 reg.h Register Address -Queue0 DCU_RETRY_LMT
819
AR5K_DCU_RETRY_LMT_SH_RETRYAR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f reg.h Short retry limit mask
820
AR5K_DCU_RETRY_LMT_SH_RETRY_SAR5K_DCU_RETRY_LMT_SH_RETRY_S 0 reg.h  
821
AR5K_DCU_RETRY_LMT_LG_RETRYAR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 reg.h Long retry limit mask
822
AR5K_DCU_RETRY_LMT_LG_RETRY_SAR5K_DCU_RETRY_LMT_LG_RETRY_S 4 reg.h  
823
AR5K_DCU_RETRY_LMT_SSH_RETRYAR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 reg.h Station short retry limit mask (?)
824
AR5K_DCU_RETRY_LMT_SSH_RETRY_SAR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 reg.h  
825
AR5K_DCU_RETRY_LMT_SLG_RETRYAR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 reg.h Station long retry limit mask (?)
826
AR5K_DCU_RETRY_LMT_SLG_RETRY_SAR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 reg.h  
827
AR5K_DCU_CHAN_TIME_BASEAR5K_DCU_CHAN_TIME_BASE 0x10c0 reg.h Register Address -Queue0 DCU_CHAN_TIME
828
AR5K_DCU_CHAN_TIME_DURAR5K_DCU_CHAN_TIME_DUR 0x000fffff reg.h Channel time duration
829
AR5K_DCU_CHAN_TIME_DUR_SAR5K_DCU_CHAN_TIME_DUR_S 0 reg.h  
830
AR5K_DCU_CHAN_TIME_ENABLEAR5K_DCU_CHAN_TIME_ENABLE 0x00100000 reg.h Enable channel time
831
AR5K_DCU_MISC_BASEAR5K_DCU_MISC_BASE 0x1100 reg.h Register Address -Queue0 DCU_MISC
832
AR5K_DCU_MISC_BACKOFFAR5K_DCU_MISC_BACKOFF 0x0000003f reg.h Mask for backoff threshold
833
AR5K_DCU_MISC_ETS_RTS_POLAR5K_DCU_MISC_ETS_RTS_POL 0x00000040 reg.h End of transmission series
834
AR5K_DCU_MISC_ETS_CW_POLAR5K_DCU_MISC_ETS_CW_POL 0x00000080 reg.h End of transmission series
835
AR5K_DCU_MISC_FRAG_WAITAR5K_DCU_MISC_FRAG_WAIT 0x00000100 reg.h Wait for next fragment
836
AR5K_DCU_MISC_BACKOFF_FRAGAR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 reg.h Enable backoff while bursting
837
AR5K_DCU_MISC_HCFPOLL_ENABLEAR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 reg.h CF - Poll enable
838
AR5K_DCU_MISC_BACKOFF_PERSISTAR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 reg.h Persistent backoff
839
AR5K_DCU_MISC_FRMPRFTCH_ENABLEAR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 reg.h Enable frame pre-fetch
840
AR5K_DCU_MISC_VIRTCOLAR5K_DCU_MISC_VIRTCOL 0x0000c000 reg.h Mask for Virtual Collision (?)
841
AR5K_DCU_MISC_VIRTCOL_NORMALAR5K_DCU_MISC_VIRTCOL_NORMAL 0 reg.h  
842
AR5K_DCU_MISC_VIRTCOL_IGNOREAR5K_DCU_MISC_VIRTCOL_IGNORE 1 reg.h  
843
AR5K_DCU_MISC_BCN_ENABLEAR5K_DCU_MISC_BCN_ENABLE 0x00010000 reg.h Enable Beacon use
844
AR5K_DCU_MISC_ARBLOCK_CTLAR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 reg.h Arbiter lockout control mask
845
AR5K_DCU_MISC_ARBLOCK_CTL_SAR5K_DCU_MISC_ARBLOCK_CTL_S 17 reg.h  
846
AR5K_DCU_MISC_ARBLOCK_CTL_NONEAR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 reg.h No arbiter lockout
847
AR5K_DCU_MISC_ARBLOCK_CTL_INTFRAR5K_DCU_MISC_ARBLOCK_CTL_INTFR 1 reg.h Intra-frame lockout
848
AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAAR5K_DCU_MISC_ARBLOCK_CTL_GLOBA 2 reg.h Global lockout
849
AR5K_DCU_MISC_ARBLOCK_IGNOREAR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 reg.h Ignore Arbiter lockout
850
AR5K_DCU_MISC_SEQ_NUM_INCR_DISAR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 reg.h Disable sequence number increment
851
AR5K_DCU_MISC_POST_FR_BKOFF_DISAR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 reg.h Disable post-frame backoff
852
AR5K_DCU_MISC_VIRT_COLL_POLICYAR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 reg.h Virtual Collision cw policy
853
AR5K_DCU_MISC_BLOWN_IFS_POLICYAR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 reg.h Blown IFS policy (?)
854
AR5K_DCU_MISC_SEQNUM_CTLAR5K_DCU_MISC_SEQNUM_CTL 0x01000000 reg.h Sequence number control (?)
855
AR5K_DCU_SEQNUM_BASEAR5K_DCU_SEQNUM_BASE 0x1140 reg.h  
856
AR5K_DCU_SEQNUM_MAR5K_DCU_SEQNUM_M 0x00000fff reg.h  
857
AR5K_DCU_GBL_IFS_SIFSAR5K_DCU_GBL_IFS_SIFS 0x1030 reg.h  
858
AR5K_DCU_GBL_IFS_SIFS_MAR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff reg.h  
859
AR5K_DCU_GBL_IFS_SLOTAR5K_DCU_GBL_IFS_SLOT 0x1070 reg.h  
860
AR5K_DCU_GBL_IFS_SLOT_MAR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff reg.h  
861
AR5K_DCU_GBL_IFS_EIFSAR5K_DCU_GBL_IFS_EIFS 0x10b0 reg.h  
862
AR5K_DCU_GBL_IFS_EIFS_MAR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff reg.h  
863
AR5K_DCU_GBL_IFS_MISCAR5K_DCU_GBL_IFS_MISC 0x10f0 reg.h Register Address
864
AR5K_DCU_GBL_IFS_MISC_LFSR_SLICAR5K_DCU_GBL_IFS_MISC_LFSR_SLIC 0x00000007 reg.h LFSR Slice Select
865
AR5K_DCU_GBL_IFS_MISC_TURBO_MODAR5K_DCU_GBL_IFS_MISC_TURBO_MOD 0x00000008 reg.h Turbo mode
866
AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_ 0x000003f0 reg.h SIFS Duration mask
867
AR5K_DCU_GBL_IFS_MISC_USEC_DURAR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 reg.h USEC Duration mask
868
AR5K_DCU_GBL_IFS_MISC_USEC_DUR_AR5K_DCU_GBL_IFS_MISC_USEC_DUR_ 10 reg.h  
869
AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DAR5K_DCU_GBL_IFS_MISC_DCU_ARB_D 0x00300000 reg.h DCU Arbiter delay mask
870
AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_ 0x00400000 reg.h SIFS cnt reset policy (?)
871
AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_ 0x00800000 reg.h AIFS cnt reset policy (?)
872
AR5K_DCU_GBL_IFS_MISC_RND_LFSR_AR5K_DCU_GBL_IFS_MISC_RND_LFSR_ 0x01000000 reg.h Disable random LFSR slice
873
AR5K_DCU_FPAR5K_DCU_FP 0x1230 reg.h Register Address
874
AR5K_DCU_FP_NOBURST_DCU_ENAR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 reg.h Enable non-burst prefetch on DCU (?)
875
AR5K_DCU_FP_NOBURST_ENAR5K_DCU_FP_NOBURST_EN 0x00000010 reg.h Enable non-burst prefetch (?)
876
AR5K_DCU_FP_BURST_DCU_ENAR5K_DCU_FP_BURST_DCU_EN 0x00000020 reg.h Enable burst prefetch on DCU (?)
877
AR5K_DCU_TXPAR5K_DCU_TXP 0x1270 reg.h Register Address
878
AR5K_DCU_TXP_MAR5K_DCU_TXP_M 0x000003ff reg.h Tx pause mask
879
AR5K_DCU_TXP_STATUSAR5K_DCU_TXP_STATUS 0x00010000 reg.h Tx pause status
880
AR5K_DCU_TX_FILTER_0_BASEAR5K_DCU_TX_FILTER_0_BASE 0x1038 reg.h  
881
AR5K_DCU_TX_FILTER_1_BASEAR5K_DCU_TX_FILTER_1_BASE 0x103c reg.h  
882
AR5K_DCU_TX_FILTER_CLRAR5K_DCU_TX_FILTER_CLR 0x143c reg.h  
883
AR5K_DCU_TX_FILTER_SETAR5K_DCU_TX_FILTER_SET 0x147c reg.h  
884
AR5K_RESET_CTLAR5K_RESET_CTL 0x4000 reg.h Register Address
885
AR5K_RESET_CTL_PCUAR5K_RESET_CTL_PCU 0x00000001 reg.h Protocol Control Unit reset
886
AR5K_RESET_CTL_DMAAR5K_RESET_CTL_DMA 0x00000002 reg.h DMA (Rx/Tx) reset [5210]
887
AR5K_RESET_CTL_BASEBANDAR5K_RESET_CTL_BASEBAND 0x00000002 reg.h Baseband reset [5211+]
888
AR5K_RESET_CTL_MACAR5K_RESET_CTL_MAC 0x00000004 reg.h MAC reset (PCU+Baseband ?) [5210]
889
AR5K_RESET_CTL_PHYAR5K_RESET_CTL_PHY 0x00000008 reg.h PHY reset [5210]
890
AR5K_RESET_CTL_PCIAR5K_RESET_CTL_PCI 0x00000010 reg.h PCI Core reset (interrupts etc)
891
AR5K_SLEEP_CTLAR5K_SLEEP_CTL 0x4004 reg.h Register Address
892
AR5K_SLEEP_CTL_SLDURAR5K_SLEEP_CTL_SLDUR 0x0000ffff reg.h Sleep duration mask
893
AR5K_SLEEP_CTL_SLDUR_SAR5K_SLEEP_CTL_SLDUR_S 0 reg.h  
894
AR5K_SLEEP_CTL_SLEAR5K_SLEEP_CTL_SLE 0x00030000 reg.h Sleep enable mask
895
AR5K_SLEEP_CTL_SLE_SAR5K_SLEEP_CTL_SLE_S 16 reg.h  
896
AR5K_SLEEP_CTL_SLE_WAKEAR5K_SLEEP_CTL_SLE_WAKE 0x00000000 reg.h Force chip awake
897
AR5K_SLEEP_CTL_SLE_SLPAR5K_SLEEP_CTL_SLE_SLP 0x00010000 reg.h Force chip sleep
898
AR5K_SLEEP_CTL_SLE_ALLOWAR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 reg.h Normal sleep policy
899
AR5K_SLEEP_CTL_SLE_UNITSAR5K_SLEEP_CTL_SLE_UNITS 0x00000008 reg.h [5211+]
900
AR5K_SLEEP_CTL_DUR_TIM_POLAR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 reg.h Sleep duration timing policy
901
AR5K_SLEEP_CTL_DUR_WRITE_POLAR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 reg.h Sleep duration write policy
902
AR5K_SLEEP_CTL_SLE_POLAR5K_SLEEP_CTL_SLE_POL 0x00100000 reg.h Sleep policy mode
903
AR5K_INTPENDAR5K_INTPEND 0x4008 reg.h  
904
AR5K_INTPEND_MAR5K_INTPEND_M 0x00000001 reg.h  
905
AR5K_SFRAR5K_SFR 0x400c reg.h  
906
AR5K_SFR_ENAR5K_SFR_EN 0x00000001 reg.h  
907
AR5K_PCICFGAR5K_PCICFG 0x4010 reg.h Register Address
908
AR5K_PCICFG_EEAEAR5K_PCICFG_EEAE 0x00000001 reg.h Eeprom access enable [5210]
909
AR5K_PCICFG_SLEEP_CLOCK_ENAR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 reg.h Enable sleep clock
910
AR5K_PCICFG_CLKRUNENAR5K_PCICFG_CLKRUNEN 0x00000004 reg.h CLKRUN enable [5211+]
911
AR5K_PCICFG_EESIZEAR5K_PCICFG_EESIZE 0x00000018 reg.h Mask for EEPROM size [5211+]
912
AR5K_PCICFG_EESIZE_SAR5K_PCICFG_EESIZE_S 3 reg.h  
913
AR5K_PCICFG_EESIZE_4KAR5K_PCICFG_EESIZE_4K 0 reg.h 4K
914
AR5K_PCICFG_EESIZE_8KAR5K_PCICFG_EESIZE_8K 1 reg.h 8K
915
AR5K_PCICFG_EESIZE_16KAR5K_PCICFG_EESIZE_16K 2 reg.h 16K
916
AR5K_PCICFG_EESIZE_FAILAR5K_PCICFG_EESIZE_FAIL 3 reg.h Failed to get size [5211+]
917
AR5K_PCICFG_LEDAR5K_PCICFG_LED 0x00000060 reg.h Led status [5211+]
918
AR5K_PCICFG_LED_NONEAR5K_PCICFG_LED_NONE 0x00000000 reg.h Default [5211+]
919
AR5K_PCICFG_LED_PENDAR5K_PCICFG_LED_PEND 0x00000020 reg.h Scan / Auth pending
920
AR5K_PCICFG_LED_ASSOCAR5K_PCICFG_LED_ASSOC 0x00000040 reg.h Associated
921
AR5K_PCICFG_BUS_SELAR5K_PCICFG_BUS_SEL 0x00000380 reg.h Mask for "bus select" [5211+] (?)
922
AR5K_PCICFG_CBEFIX_DISAR5K_PCICFG_CBEFIX_DIS 0x00000400 reg.h Disable CBE fix
923
AR5K_PCICFG_SL_INTENAR5K_PCICFG_SL_INTEN 0x00000800 reg.h Enable interrupts when asleep
924
AR5K_PCICFG_LED_BCTLAR5K_PCICFG_LED_BCTL 0x00001000 reg.h Led blink (?) [5210]
925
AR5K_PCICFG_RETRY_FIXAR5K_PCICFG_RETRY_FIX 0x00001000 reg.h Enable pci core retry fix
926
AR5K_PCICFG_SL_INPENAR5K_PCICFG_SL_INPEN 0x00002000 reg.h Sleep even whith pending interrupts
927
AR5K_PCICFG_SPWR_DNAR5K_PCICFG_SPWR_DN 0x00010000 reg.h Mask for power status
928
AR5K_PCICFG_LEDMODEAR5K_PCICFG_LEDMODE 0x000e0000 reg.h Ledmode [5211+]
929
AR5K_PCICFG_LEDMODE_PROPAR5K_PCICFG_LEDMODE_PROP 0x00000000 reg.h Blink on standard traffic [5211+]
930
AR5K_PCICFG_LEDMODE_PROMAR5K_PCICFG_LEDMODE_PROM 0x00020000 reg.h Default mode (blink on any traffic) [5211+]
931
AR5K_PCICFG_LEDMODE_PWRAR5K_PCICFG_LEDMODE_PWR 0x00040000 reg.h Some other blinking mode (?) [5211+]
932
AR5K_PCICFG_LEDMODE_RANDAR5K_PCICFG_LEDMODE_RAND 0x00060000 reg.h Random blinking (?) [5211+]
933
AR5K_PCICFG_LEDBLINKAR5K_PCICFG_LEDBLINK 0x00700000 reg.h Led blink rate
934
AR5K_PCICFG_LEDBLINK_SAR5K_PCICFG_LEDBLINK_S 20 reg.h  
935
AR5K_PCICFG_LEDSLOWAR5K_PCICFG_LEDSLOW 0x00800000 reg.h Slowest led blink rate [5211+]
936
AR5K_PCICFG_LEDSTATEAR5K_PCICFG_LEDSTATE (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) reg.h  
937
AR5K_PCICFG_SLEEP_CLOCK_RATEAR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 reg.h Sleep clock rate
938
AR5K_PCICFG_SLEEP_CLOCK_RATE_SAR5K_PCICFG_SLEEP_CLOCK_RATE_S 24 reg.h  
939
AR5K_NUM_GPIOAR5K_NUM_GPIO 6 reg.h  
940
AR5K_GPIOCRAR5K_GPIOCR 0x4014 reg.h Register Address
941
AR5K_GPIOCR_INT_ENAAR5K_GPIOCR_INT_ENA 0x00008000 reg.h Enable GPIO interrupt
942
AR5K_GPIOCR_INT_SELLAR5K_GPIOCR_INT_SELL 0x00000000 reg.h Generate interrupt when pin is low
943
AR5K_GPIOCR_INT_SELHAR5K_GPIOCR_INT_SELH 0x00010000 reg.h Generate interrupt when pin is high
944
AR5K_GPIODOAR5K_GPIODO 0x4018 reg.h  
945
AR5K_GPIODIAR5K_GPIODI 0x401c reg.h  
946
AR5K_GPIODI_MAR5K_GPIODI_M 0x0000002f reg.h  
947
AR5K_SREVAR5K_SREV 0x4020 reg.h Register Address
948
AR5K_SREV_REVAR5K_SREV_REV 0x0000000f reg.h Mask for revision
949
AR5K_SREV_REV_SAR5K_SREV_REV_S 0 reg.h  
950
AR5K_SREV_VERAR5K_SREV_VER 0x000000ff reg.h Mask for version
951
AR5K_SREV_VER_SAR5K_SREV_VER_S 4 reg.h  
952
AR5K_TXEPOSTAR5K_TXEPOST 0x4028 reg.h  
953
AR5K_QCU_SLEEP_MASKAR5K_QCU_SLEEP_MASK 0x402c reg.h  
954
AR5K_5414_CBCFGAR5K_5414_CBCFG 0x4068 reg.h  
955
AR5K_5414_CBCFG_BUF_DISAR5K_5414_CBCFG_BUF_DIS 0x10 reg.h Disable buffer
956
AR5K_PCIE_PM_CTLAR5K_PCIE_PM_CTL 0x4068 reg.h Register address
957
AR5K_PCIE_PM_CTL_L1_WHEN_D2AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 reg.h enable PCIe core enter L1
958
AR5K_PCIE_PM_CTL_L0_L0S_CLEARAR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 reg.h Clear L0 and L0S counters
959
AR5K_PCIE_PM_CTL_L0_L0S_ENAR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 reg.h Start L0 nd L0S counters
960
AR5K_PCIE_PM_CTL_LDRESET_ENAR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 reg.h Enable reset when link goes
961
AR5K_PCIE_PM_CTL_PME_ENAR5K_PCIE_PM_CTL_PME_EN 0x00000010 reg.h PME Enable
962
AR5K_PCIE_PM_CTL_AUX_PWR_DETAR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 reg.h Aux power detect
963
AR5K_PCIE_PM_CTL_PME_CLEARAR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 reg.h Clear PME
964
AR5K_PCIE_PM_CTL_PSM_D0AR5K_PCIE_PM_CTL_PSM_D0 0x00000080 reg.h  
965
AR5K_PCIE_PM_CTL_PSM_D1AR5K_PCIE_PM_CTL_PSM_D1 0x00000100 reg.h  
966
AR5K_PCIE_PM_CTL_PSM_D2AR5K_PCIE_PM_CTL_PSM_D2 0x00000200 reg.h  
967
AR5K_PCIE_PM_CTL_PSM_D3AR5K_PCIE_PM_CTL_PSM_D3 0x00000400 reg.h  
968
AR5K_PCIE_WAENAR5K_PCIE_WAEN 0x407c reg.h  
969
AR5K_PCIE_SERDESAR5K_PCIE_SERDES 0x4080 reg.h  
970
AR5K_PCIE_SERDES_RESETAR5K_PCIE_SERDES_RESET 0x4084 reg.h  
971
AR5K_EEPROM_BASEAR5K_EEPROM_BASE 0x6000 reg.h  
972
AR5K_EEPROM_DATA_5211AR5K_EEPROM_DATA_5211 0x6004 reg.h  
973
AR5K_EEPROM_DATA_5210AR5K_EEPROM_DATA_5210 0x6800 reg.h  
974
AR5K_EEPROM_DATAAR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \ AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) reg.h  
975
AR5K_EEPROM_CMDAR5K_EEPROM_CMD 0x6008 reg.h Register Addres
976
AR5K_EEPROM_CMD_READAR5K_EEPROM_CMD_READ 0x00000001 reg.h EEPROM read
977
AR5K_EEPROM_CMD_WRITEAR5K_EEPROM_CMD_WRITE 0x00000002 reg.h EEPROM write
978
AR5K_EEPROM_CMD_RESETAR5K_EEPROM_CMD_RESET 0x00000004 reg.h EEPROM reset
979
AR5K_EEPROM_STAT_5210AR5K_EEPROM_STAT_5210 0x6c00 reg.h Register Address [5210]
980
AR5K_EEPROM_STAT_5211AR5K_EEPROM_STAT_5211 0x600c reg.h Register Address [5211+]
981
AR5K_EEPROM_STATUSAR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \ AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) reg.h  
982
AR5K_EEPROM_STAT_RDERRAR5K_EEPROM_STAT_RDERR 0x00000001 reg.h EEPROM read failed
983
AR5K_EEPROM_STAT_RDDONEAR5K_EEPROM_STAT_RDDONE 0x00000002 reg.h EEPROM read successful
984
AR5K_EEPROM_STAT_WRERRAR5K_EEPROM_STAT_WRERR 0x00000004 reg.h EEPROM write failed
985
AR5K_EEPROM_STAT_WRDONEAR5K_EEPROM_STAT_WRDONE 0x00000008 reg.h EEPROM write successful
986
AR5K_EEPROM_CFGAR5K_EEPROM_CFG 0x6010 reg.h Register Addres
987
AR5K_EEPROM_CFG_SIZEAR5K_EEPROM_CFG_SIZE 0x00000003 reg.h Size determination override
988
AR5K_EEPROM_CFG_SIZE_AUTOAR5K_EEPROM_CFG_SIZE_AUTO 0 reg.h  
989
AR5K_EEPROM_CFG_SIZE_4KBITAR5K_EEPROM_CFG_SIZE_4KBIT 1 reg.h  
990
AR5K_EEPROM_CFG_SIZE_8KBITAR5K_EEPROM_CFG_SIZE_8KBIT 2 reg.h  
991
AR5K_EEPROM_CFG_SIZE_16KBITAR5K_EEPROM_CFG_SIZE_16KBIT 3 reg.h  
992
AR5K_EEPROM_CFG_WR_WAIT_DISAR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 reg.h Disable write wait
993
AR5K_EEPROM_CFG_CLK_RATEAR5K_EEPROM_CFG_CLK_RATE 0x00000018 reg.h Clock rate
994
AR5K_EEPROM_CFG_CLK_RATE_SAR5K_EEPROM_CFG_CLK_RATE_S 3 reg.h  
995
AR5K_EEPROM_CFG_CLK_RATE_156KHZAR5K_EEPROM_CFG_CLK_RATE_156KHZ 0 reg.h  
996
AR5K_EEPROM_CFG_CLK_RATE_312KHZAR5K_EEPROM_CFG_CLK_RATE_312KHZ 1 reg.h  
997
AR5K_EEPROM_CFG_CLK_RATE_625KHZAR5K_EEPROM_CFG_CLK_RATE_625KHZ 2 reg.h  
998
AR5K_EEPROM_CFG_PROT_KEYAR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 reg.h Protection key
999
AR5K_EEPROM_CFG_PROT_KEY_SAR5K_EEPROM_CFG_PROT_KEY_S 8 reg.h  
1000
AR5K_EEPROM_CFG_LIND_ENAR5K_EEPROM_CFG_LIND_EN 0x01000000 reg.h Enable length indicator (?)
1001
AR5K_PCU_MINAR5K_PCU_MIN 0x8000 reg.h  
1002
AR5K_PCU_MAXAR5K_PCU_MAX 0x8fff reg.h  
1003
AR5K_STA_ID0AR5K_STA_ID0 0x8000 reg.h  
1004
AR5K_STA_ID0_ARRD_L32AR5K_STA_ID0_ARRD_L32 0xffffffff reg.h  
1005
AR5K_STA_ID1AR5K_STA_ID1 0x8004 reg.h Register Address
1006
AR5K_STA_ID1_ADDR_U16AR5K_STA_ID1_ADDR_U16 0x0000ffff reg.h Upper 16 bits of MAC addres
1007
AR5K_STA_ID1_APAR5K_STA_ID1_AP 0x00010000 reg.h Set AP mode
1008
AR5K_STA_ID1_ADHOCAR5K_STA_ID1_ADHOC 0x00020000 reg.h Set Ad-Hoc mode
1009
AR5K_STA_ID1_PWR_SVAR5K_STA_ID1_PWR_SV 0x00040000 reg.h Power save reporting
1010
AR5K_STA_ID1_NO_KEYSRCHAR5K_STA_ID1_NO_KEYSRCH 0x00080000 reg.h No key search
1011
AR5K_STA_ID1_NO_PSPOLLAR5K_STA_ID1_NO_PSPOLL 0x00100000 reg.h No power save polling [5210]
1012
AR5K_STA_ID1_PCF_5211AR5K_STA_ID1_PCF_5211 0x00100000 reg.h Enable PCF on [5211+]
1013
AR5K_STA_ID1_PCF_5210AR5K_STA_ID1_PCF_5210 0x00200000 reg.h Enable PCF on [5210]
1014
AR5K_STA_ID1_PCFAR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \ AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) reg.h  
1015
AR5K_STA_ID1_DEFAULT_ANTENNAAR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 reg.h Use default antenna
1016
AR5K_STA_ID1_DESC_ANTENNAAR5K_STA_ID1_DESC_ANTENNA 0x00400000 reg.h Update antenna from descriptor
1017
AR5K_STA_ID1_RTS_DEF_ANTENNAAR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 reg.h Use default antenna for RTS
1018
AR5K_STA_ID1_ACKCTS_6MBAR5K_STA_ID1_ACKCTS_6MB 0x01000000 reg.h Use 6Mbit/s for ACK/CTS
1019
AR5K_STA_ID1_BASE_RATE_11BAR5K_STA_ID1_BASE_RATE_11B 0x02000000 reg.h Use 11b base rate for ACK/CTS [5211+]
1020
AR5K_STA_ID1_SELFGEN_DEF_ANTAR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 reg.h Use def. antenna for self generated frames
1021
AR5K_STA_ID1_CRYPT_MIC_ENAR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 reg.h Enable MIC
1022
AR5K_STA_ID1_KEYSRCH_MODEAR5K_STA_ID1_KEYSRCH_MODE 0x10000000 reg.h Look up key when key id != 0
1023
AR5K_STA_ID1_PRESERVE_SEQ_NUMAR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 reg.h Preserve sequence number
1024
AR5K_STA_ID1_CBCIV_ENDIANAR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 reg.h ???
1025
AR5K_STA_ID1_KEYSRCH_MCASTAR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 reg.h Do key cache search for mcast frames
1026
AR5K_BSS_ID0AR5K_BSS_ID0 0x8008 reg.h  
1027
AR5K_BSS_ID1AR5K_BSS_ID1 0x800c reg.h  
1028
AR5K_BSS_ID1_AIDAR5K_BSS_ID1_AID 0xffff0000 reg.h  
1029
AR5K_BSS_ID1_AID_SAR5K_BSS_ID1_AID_S 16 reg.h  
1030
AR5K_SLOT_TIMEAR5K_SLOT_TIME 0x8010 reg.h  
1031
AR5K_TIME_OUTAR5K_TIME_OUT 0x8014 reg.h Register Address
1032
AR5K_TIME_OUT_ACKAR5K_TIME_OUT_ACK 0x00001fff reg.h ACK timeout mask
1033
AR5K_TIME_OUT_ACK_SAR5K_TIME_OUT_ACK_S 0 reg.h  
1034
AR5K_TIME_OUT_CTSAR5K_TIME_OUT_CTS 0x1fff0000 reg.h CTS timeout mask
1035
AR5K_TIME_OUT_CTS_SAR5K_TIME_OUT_CTS_S 16 reg.h  
1036
AR5K_RSSI_THRAR5K_RSSI_THR 0x8018 reg.h Register Address
1037
AR5K_RSSI_THR_MAR5K_RSSI_THR_M 0x000000ff reg.h Mask for RSSI threshold [5211+]
1038
AR5K_RSSI_THR_BMISS_5210AR5K_RSSI_THR_BMISS_5210 0x00000700 reg.h Mask for Beacon Missed threshold [5210]
1039
AR5K_RSSI_THR_BMISS_5210_SAR5K_RSSI_THR_BMISS_5210_S 8 reg.h  
1040
AR5K_RSSI_THR_BMISS_5211AR5K_RSSI_THR_BMISS_5211 0x0000ff00 reg.h Mask for Beacon Missed threshold [5211+]
1041
AR5K_RSSI_THR_BMISS_5211_SAR5K_RSSI_THR_BMISS_5211_S 8 reg.h  
1042
AR5K_RSSI_THR_BMISSAR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \ AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) reg.h  
1043
AR5K_RSSI_THR_BMISS_SAR5K_RSSI_THR_BMISS_S 8 reg.h  
1044
AR5K_NODCU_RETRY_LMTAR5K_NODCU_RETRY_LMT 0x801c reg.h Register Address
1045
AR5K_NODCU_RETRY_LMT_SH_RETRYAR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f reg.h Short retry limit mask
1046
AR5K_NODCU_RETRY_LMT_SH_RETRY_SAR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 reg.h  
1047
AR5K_NODCU_RETRY_LMT_LG_RETRYAR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 reg.h Long retry mask
1048
AR5K_NODCU_RETRY_LMT_LG_RETRY_SAR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 reg.h  
1049
AR5K_NODCU_RETRY_LMT_SSH_RETRYAR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 reg.h Station short retry limit mask
1050
AR5K_NODCU_RETRY_LMT_SSH_RETRY_AR5K_NODCU_RETRY_LMT_SSH_RETRY_ 8 reg.h  
1051
AR5K_NODCU_RETRY_LMT_SLG_RETRYAR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 reg.h Station long retry limit mask
1052
AR5K_NODCU_RETRY_LMT_SLG_RETRY_AR5K_NODCU_RETRY_LMT_SLG_RETRY_ 14 reg.h  
1053
AR5K_NODCU_RETRY_LMT_CW_MINAR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 reg.h Minimum contention window mask
1054
AR5K_NODCU_RETRY_LMT_CW_MIN_SAR5K_NODCU_RETRY_LMT_CW_MIN_S 20 reg.h  
1055
AR5K_USEC_5210AR5K_USEC_5210 0x8020 reg.h Register Address [5210]
1056
AR5K_USEC_5211AR5K_USEC_5211 0x801c reg.h Register Address [5211+]
1057
AR5K_USECAR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ AR5K_USEC_5210 : AR5K_USEC_5211) reg.h  
1058
AR5K_USEC_1AR5K_USEC_1 0x0000007f reg.h clock cycles for 1us
1059
AR5K_USEC_1_SAR5K_USEC_1_S 0 reg.h  
1060
AR5K_USEC_32AR5K_USEC_32 0x00003f80 reg.h clock cycles for 1us while on 32Mhz clock
1061
AR5K_USEC_32_SAR5K_USEC_32_S 7 reg.h  
1062
AR5K_USEC_TX_LATENCY_5211AR5K_USEC_TX_LATENCY_5211 0x007fc000 reg.h  
1063
AR5K_USEC_TX_LATENCY_5211_SAR5K_USEC_TX_LATENCY_5211_S 14 reg.h  
1064
AR5K_USEC_RX_LATENCY_5211AR5K_USEC_RX_LATENCY_5211 0x1f800000 reg.h  
1065
AR5K_USEC_RX_LATENCY_5211_SAR5K_USEC_RX_LATENCY_5211_S 23 reg.h  
1066
AR5K_USEC_TX_LATENCY_5210AR5K_USEC_TX_LATENCY_5210 0x000fc000 reg.h also for 5311
1067
AR5K_USEC_TX_LATENCY_5210_SAR5K_USEC_TX_LATENCY_5210_S 14 reg.h  
1068
AR5K_USEC_RX_LATENCY_5210AR5K_USEC_RX_LATENCY_5210 0x03f00000 reg.h also for 5311
1069
AR5K_USEC_RX_LATENCY_5210_SAR5K_USEC_RX_LATENCY_5210_S 20 reg.h  
1070
AR5K_BEACON_5210AR5K_BEACON_5210 0x8024 reg.h Register Address [5210]
1071
AR5K_BEACON_5211AR5K_BEACON_5211 0x8020 reg.h Register Address [5211+]
1072
AR5K_BEACONAR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ AR5K_BEACON_5210 : AR5K_BEACON_5211) reg.h  
1073
AR5K_BEACON_PERIODAR5K_BEACON_PERIOD 0x0000ffff reg.h Mask for beacon period
1074
AR5K_BEACON_PERIOD_SAR5K_BEACON_PERIOD_S 0 reg.h  
1075
AR5K_BEACON_TIMAR5K_BEACON_TIM 0x007f0000 reg.h Mask for TIM offset
1076
AR5K_BEACON_TIM_SAR5K_BEACON_TIM_S 16 reg.h  
1077
AR5K_BEACON_ENABLEAR5K_BEACON_ENABLE 0x00800000 reg.h Enable beacons
1078
AR5K_BEACON_RESET_TSFAR5K_BEACON_RESET_TSF 0x01000000 reg.h Force TSF reset
1079
AR5K_CFP_PERIOD_5210AR5K_CFP_PERIOD_5210 0x8028 reg.h  
1080
AR5K_CFP_PERIOD_5211AR5K_CFP_PERIOD_5211 0x8024 reg.h  
1081
AR5K_CFP_PERIODAR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \ AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) reg.h  
1082
AR5K_TIMER0_5210AR5K_TIMER0_5210 0x802c reg.h  
1083
AR5K_TIMER0_5211AR5K_TIMER0_5211 0x8028 reg.h  
1084
AR5K_TIMER0AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER0_5210 : AR5K_TIMER0_5211) reg.h  
1085
AR5K_TIMER1_5210AR5K_TIMER1_5210 0x8030 reg.h  
1086
AR5K_TIMER1_5211AR5K_TIMER1_5211 0x802c reg.h  
1087
AR5K_TIMER1AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER1_5210 : AR5K_TIMER1_5211) reg.h  
1088
AR5K_TIMER2_5210AR5K_TIMER2_5210 0x8034 reg.h  
1089
AR5K_TIMER2_5211AR5K_TIMER2_5211 0x8030 reg.h  
1090
AR5K_TIMER2AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER2_5210 : AR5K_TIMER2_5211) reg.h  
1091
AR5K_TIMER3_5210AR5K_TIMER3_5210 0x8038 reg.h  
1092
AR5K_TIMER3_5211AR5K_TIMER3_5211 0x8034 reg.h  
1093
AR5K_TIMER3AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER3_5210 : AR5K_TIMER3_5211) reg.h  
1094
AR5K_IFS0AR5K_IFS0 0x8040 reg.h  
1095
AR5K_IFS0_SIFSAR5K_IFS0_SIFS 0x000007ff reg.h  
1096
AR5K_IFS0_SIFS_SAR5K_IFS0_SIFS_S 0 reg.h  
1097
AR5K_IFS0_DIFSAR5K_IFS0_DIFS 0x007ff800 reg.h  
1098
AR5K_IFS0_DIFS_SAR5K_IFS0_DIFS_S 11 reg.h  
1099
AR5K_IFS1AR5K_IFS1 0x8044 reg.h  
1100
AR5K_IFS1_PIFSAR5K_IFS1_PIFS 0x00000fff reg.h  
1101
AR5K_IFS1_PIFS_SAR5K_IFS1_PIFS_S 0 reg.h  
1102
AR5K_IFS1_EIFSAR5K_IFS1_EIFS 0x03fff000 reg.h  
1103
AR5K_IFS1_EIFS_SAR5K_IFS1_EIFS_S 12 reg.h  
1104
AR5K_IFS1_CS_ENAR5K_IFS1_CS_EN 0x04000000 reg.h  
1105
AR5K_CFP_DUR_5210AR5K_CFP_DUR_5210 0x8048 reg.h  
1106
AR5K_CFP_DUR_5211AR5K_CFP_DUR_5211 0x8038 reg.h  
1107
AR5K_CFP_DURAR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \ AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) reg.h  
1108
AR5K_RX_FILTER_5210AR5K_RX_FILTER_5210 0x804c reg.h Register Address [5210]
1109
AR5K_RX_FILTER_5211AR5K_RX_FILTER_5211 0x803c reg.h Register Address [5211+]
1110
AR5K_RX_FILTERAR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) reg.h  
1111
AR5K_RX_FILTER_UCASTAR5K_RX_FILTER_UCAST 0x00000001 reg.h Don't filter unicast frames
1112
AR5K_RX_FILTER_MCASTAR5K_RX_FILTER_MCAST 0x00000002 reg.h Don't filter multicast frames
1113
AR5K_RX_FILTER_BCASTAR5K_RX_FILTER_BCAST 0x00000004 reg.h Don't filter broadcast frames
1114
AR5K_RX_FILTER_CONTROLAR5K_RX_FILTER_CONTROL 0x00000008 reg.h Don't filter control frames
1115
AR5K_RX_FILTER_BEACONAR5K_RX_FILTER_BEACON 0x00000010 reg.h Don't filter beacon frames
1116
AR5K_RX_FILTER_PROMAR5K_RX_FILTER_PROM 0x00000020 reg.h Set promiscuous mode
1117
AR5K_RX_FILTER_XRPOLLAR5K_RX_FILTER_XRPOLL 0x00000040 reg.h Don't filter XR poll frame [5212+]
1118
AR5K_RX_FILTER_PROBEREQAR5K_RX_FILTER_PROBEREQ 0x00000080 reg.h Don't filter probe requests [5212+]
1119
AR5K_RX_FILTER_PHYERR_5212AR5K_RX_FILTER_PHYERR_5212 0x00000100 reg.h Don't filter phy errors [5212+]
1120
AR5K_RX_FILTER_RADARERR_5212AR5K_RX_FILTER_RADARERR_5212 0x00000200 reg.h Don't filter phy radar errors [5212+]
1121
AR5K_RX_FILTER_PHYERR_5211AR5K_RX_FILTER_PHYERR_5211 0x00000040 reg.h [5211]
1122
AR5K_RX_FILTER_RADARERR_5211AR5K_RX_FILTER_RADARERR_5211 0x00000080 reg.h [5211]
1123
AR5K_RX_FILTER_PHYERRAR5K_RX_FILTER_PHYERR ((ah->ah_version == AR5K_AR5211 ? \ AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212)) reg.h  
1124
AR5K_RX_FILTER_RADARERRAR5K_RX_FILTER_RADARERR ((ah->ah_version == AR5K_AR5211 ? \ AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212)) reg.h  
1125
AR5K_MCAST_FILTER0_5210AR5K_MCAST_FILTER0_5210 0x8050 reg.h  
1126
AR5K_MCAST_FILTER0_5211AR5K_MCAST_FILTER0_5211 0x8040 reg.h  
1127
AR5K_MCAST_FILTER0AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \ AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) reg.h  
1128
AR5K_MCAST_FILTER1_5210AR5K_MCAST_FILTER1_5210 0x8054 reg.h  
1129
AR5K_MCAST_FILTER1_5211AR5K_MCAST_FILTER1_5211 0x8044 reg.h  
1130
AR5K_MCAST_FILTER1AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \ AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) reg.h  
1131
AR5K_TX_MASK0AR5K_TX_MASK0 0x8058 reg.h  
1132
AR5K_TX_MASK1AR5K_TX_MASK1 0x805c reg.h  
1133
AR5K_CLR_TMASKAR5K_CLR_TMASK 0x8060 reg.h  
1134
AR5K_TRIG_LVLAR5K_TRIG_LVL 0x8064 reg.h  
1135
AR5K_DIAG_SW_5210AR5K_DIAG_SW_5210 0x8068 reg.h Register Address [5210]
1136
AR5K_DIAG_SW_5211AR5K_DIAG_SW_5211 0x8048 reg.h Register Address [5211+]
1137
AR5K_DIAG_SWAR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) reg.h  
1138
AR5K_DIAG_SW_DIS_WEP_ACKAR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 reg.h Disable ACKs if WEP key is invalid
1139
AR5K_DIAG_SW_DIS_ACKAR5K_DIAG_SW_DIS_ACK 0x00000002 reg.h Disable ACKs
1140
AR5K_DIAG_SW_DIS_CTSAR5K_DIAG_SW_DIS_CTS 0x00000004 reg.h Disable CTSs
1141
AR5K_DIAG_SW_DIS_ENCAR5K_DIAG_SW_DIS_ENC 0x00000008 reg.h Disable encryption
1142
AR5K_DIAG_SW_DIS_DECAR5K_DIAG_SW_DIS_DEC 0x00000010 reg.h Disable decryption
1143
AR5K_DIAG_SW_DIS_TXAR5K_DIAG_SW_DIS_TX 0x00000020 reg.h Disable transmit [5210]
1144
AR5K_DIAG_SW_DIS_RX_5210AR5K_DIAG_SW_DIS_RX_5210 0x00000040 reg.h Disable recieve
1145
AR5K_DIAG_SW_DIS_RX_5211AR5K_DIAG_SW_DIS_RX_5211 0x00000020 reg.h  
1146
AR5K_DIAG_SW_DIS_RXAR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) reg.h  
1147
AR5K_DIAG_SW_LOOP_BACK_5210AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 reg.h Loopback (i guess it goes with DIS_TX) [5210]
1148
AR5K_DIAG_SW_LOOP_BACK_5211AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 reg.h  
1149
AR5K_DIAG_SW_LOOP_BACKAR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) reg.h  
1150
AR5K_DIAG_SW_CORR_FCS_5210AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 reg.h Corrupted FCS
1151
AR5K_DIAG_SW_CORR_FCS_5211AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 reg.h  
1152
AR5K_DIAG_SW_CORR_FCSAR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) reg.h  
1153
AR5K_DIAG_SW_CHAN_INFO_5210AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 reg.h Dump channel info
1154
AR5K_DIAG_SW_CHAN_INFO_5211AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 reg.h  
1155
AR5K_DIAG_SW_CHAN_INFOAR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) reg.h  
1156
AR5K_DIAG_SW_EN_SCRAM_SEED_5210AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 reg.h Enable fixed scrambler seed
1157
AR5K_DIAG_SW_EN_SCRAM_SEED_5211AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 reg.h  
1158
AR5K_DIAG_SW_EN_SCRAM_SEEDAR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) reg.h  
1159
AR5K_DIAG_SW_ECO_ENABLEAR5K_DIAG_SW_ECO_ENABLE 0x00000400 reg.h [5211+]
1160
AR5K_DIAG_SW_SCVRAM_SEEDAR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 reg.h [5210]
1161
AR5K_DIAG_SW_SCRAM_SEED_MAR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 reg.h Scrambler seed mask
1162
AR5K_DIAG_SW_SCRAM_SEED_SAR5K_DIAG_SW_SCRAM_SEED_S 10 reg.h  
1163
AR5K_DIAG_SW_DIS_SEQ_INCAR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 reg.h Disable seqnum increment (?)[5210]
1164
AR5K_DIAG_SW_FRAME_NV0_5210AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 reg.h  
1165
AR5K_DIAG_SW_FRAME_NV0_5211AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 reg.h Accept frames of non-zero protocol number
1166
AR5K_DIAG_SW_FRAME_NV0AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) reg.h  
1167
AR5K_DIAG_SW_OBSPT_MAR5K_DIAG_SW_OBSPT_M 0x000c0000 reg.h Observation point select (?)
1168
AR5K_DIAG_SW_OBSPT_SAR5K_DIAG_SW_OBSPT_S 18 reg.h  
1169
AR5K_DIAG_SW_RX_CLEAR_HIGHAR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000 reg.h Force RX Clear high
1170
AR5K_DIAG_SW_IGNORE_CARR_SENSEAR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000 reg.h Ignore virtual carrier sense
1171
AR5K_DIAG_SW_CHANEL_IDLE_HIGHAR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000 reg.h Force channel idle high
1172
AR5K_DIAG_SW_PHEAR_MEAR5K_DIAG_SW_PHEAR_ME 0x0080000 reg.h ???
1173
AR5K_TSF_L32_5210AR5K_TSF_L32_5210 0x806c reg.h  
1174
AR5K_TSF_L32_5211AR5K_TSF_L32_5211 0x804c reg.h  
1175
AR5K_TSF_L32AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) reg.h  
1176
AR5K_TSF_U32_5210AR5K_TSF_U32_5210 0x8070 reg.h  
1177
AR5K_TSF_U32_5211AR5K_TSF_U32_5211 0x8050 reg.h  
1178
AR5K_TSF_U32AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) reg.h  
1179
AR5K_LAST_TSTPAR5K_LAST_TSTP 0x8080 reg.h  
1180
AR5K_ADDAC_TESTAR5K_ADDAC_TEST 0x8054 reg.h Register Address
1181
AR5K_ADDAC_TEST_TXCONTAR5K_ADDAC_TEST_TXCONT 0x00000001 reg.h Test continuous tx
1182
AR5K_ADDAC_TEST_TST_MODEAR5K_ADDAC_TEST_TST_MODE 0x00000002 reg.h Test mode
1183
AR5K_ADDAC_TEST_LOOP_ENAR5K_ADDAC_TEST_LOOP_EN 0x00000004 reg.h Enable loop
1184
AR5K_ADDAC_TEST_LOOP_LENAR5K_ADDAC_TEST_LOOP_LEN 0x00000008 reg.h Loop length (field)
1185
AR5K_ADDAC_TEST_USE_U8AR5K_ADDAC_TEST_USE_U8 0x00004000 reg.h Use upper 8 bits
1186
AR5K_ADDAC_TEST_MSBAR5K_ADDAC_TEST_MSB 0x00008000 reg.h State of MSB
1187
AR5K_ADDAC_TEST_TRIG_SELAR5K_ADDAC_TEST_TRIG_SEL 0x00010000 reg.h Trigger select
1188
AR5K_ADDAC_TEST_TRIG_PTYAR5K_ADDAC_TEST_TRIG_PTY 0x00020000 reg.h Trigger polarity
1189
AR5K_ADDAC_TEST_RXCONTAR5K_ADDAC_TEST_RXCONT 0x00040000 reg.h Continuous capture
1190
AR5K_ADDAC_TEST_CAPTUREAR5K_ADDAC_TEST_CAPTURE 0x00080000 reg.h Begin capture
1191
AR5K_ADDAC_TEST_TST_ARMAR5K_ADDAC_TEST_TST_ARM 0x00100000 reg.h ARM rx buffer for capture
1192
AR5K_DEFAULT_ANTENNAAR5K_DEFAULT_ANTENNA 0x8058 reg.h  
1193
AR5K_FRAME_CTL_QOSMAR5K_FRAME_CTL_QOSM 0x805c reg.h  
1194
AR5K_SEQ_MASKAR5K_SEQ_MASK 0x8060 reg.h  
1195
AR5K_RETRY_CNTAR5K_RETRY_CNT 0x8084 reg.h Register Address [5210]
1196
AR5K_RETRY_CNT_SSHAR5K_RETRY_CNT_SSH 0x0000003f reg.h Station short retry count (?)
1197
AR5K_RETRY_CNT_SLGAR5K_RETRY_CNT_SLG 0x00000fc0 reg.h Station long retry count (?)
1198
AR5K_BACKOFFAR5K_BACKOFF 0x8088 reg.h Register Address [5210]
1199
AR5K_BACKOFF_CWAR5K_BACKOFF_CW 0x000003ff reg.h Backoff Contention Window (?)
1200
AR5K_BACKOFF_CNTAR5K_BACKOFF_CNT 0x03ff0000 reg.h Backoff count (?)
1201
AR5K_NAV_5210AR5K_NAV_5210 0x808c reg.h  
1202
AR5K_NAV_5211AR5K_NAV_5211 0x8084 reg.h  
1203
AR5K_NAVAR5K_NAV (ah->ah_version == AR5K_AR5210 ? \ AR5K_NAV_5210 : AR5K_NAV_5211) reg.h  
1204
AR5K_RTS_OK_5210AR5K_RTS_OK_5210 0x8090 reg.h  
1205
AR5K_RTS_OK_5211AR5K_RTS_OK_5211 0x8088 reg.h  
1206
AR5K_RTS_OKAR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \ AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) reg.h  
1207
AR5K_RTS_FAIL_5210AR5K_RTS_FAIL_5210 0x8094 reg.h  
1208
AR5K_RTS_FAIL_5211AR5K_RTS_FAIL_5211 0x808c reg.h  
1209
AR5K_RTS_FAILAR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \ AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) reg.h  
1210
AR5K_ACK_FAIL_5210AR5K_ACK_FAIL_5210 0x8098 reg.h  
1211
AR5K_ACK_FAIL_5211AR5K_ACK_FAIL_5211 0x8090 reg.h  
1212
AR5K_ACK_FAILAR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \ AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) reg.h  
1213
AR5K_FCS_FAIL_5210AR5K_FCS_FAIL_5210 0x809c reg.h  
1214
AR5K_FCS_FAIL_5211AR5K_FCS_FAIL_5211 0x8094 reg.h  
1215
AR5K_FCS_FAILAR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \ AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) reg.h  
1216
AR5K_BEACON_CNT_5210AR5K_BEACON_CNT_5210 0x80a0 reg.h  
1217
AR5K_BEACON_CNT_5211AR5K_BEACON_CNT_5211 0x8098 reg.h  
1218
AR5K_BEACON_CNTAR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \ AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) reg.h  
1219
AR5K_TPCAR5K_TPC 0x80e8 reg.h  
1220
AR5K_TPC_ACKAR5K_TPC_ACK 0x0000003f reg.h ack frames
1221
AR5K_TPC_ACK_SAR5K_TPC_ACK_S 0 reg.h  
1222
AR5K_TPC_CTSAR5K_TPC_CTS 0x00003f00 reg.h cts frames
1223
AR5K_TPC_CTS_SAR5K_TPC_CTS_S 8 reg.h  
1224
AR5K_TPC_CHIRPAR5K_TPC_CHIRP 0x003f0000 reg.h chirp frames
1225
AR5K_TPC_CHIRP_SAR5K_TPC_CHIRP_S 16 reg.h  
1226
AR5K_TPC_DOPPLERAR5K_TPC_DOPPLER 0x0f000000 reg.h doppler chirp span
1227
AR5K_TPC_DOPPLER_SAR5K_TPC_DOPPLER_S 24 reg.h  
1228
AR5K_XRMODEAR5K_XRMODE 0x80c0 reg.h Register Address
1229
AR5K_XRMODE_POLL_TYPE_MAR5K_XRMODE_POLL_TYPE_M 0x0000003f reg.h Mask for Poll type (?)
1230
AR5K_XRMODE_POLL_TYPE_SAR5K_XRMODE_POLL_TYPE_S 0 reg.h  
1231
AR5K_XRMODE_POLL_SUBTYPE_MAR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c reg.h Mask for Poll subtype (?)
1232
AR5K_XRMODE_POLL_SUBTYPE_SAR5K_XRMODE_POLL_SUBTYPE_S 2 reg.h  
1233
AR5K_XRMODE_POLL_WAIT_ALLAR5K_XRMODE_POLL_WAIT_ALL 0x00000080 reg.h Wait for poll
1234
AR5K_XRMODE_SIFS_DELAYAR5K_XRMODE_SIFS_DELAY 0x000fff00 reg.h Mask for SIFS delay
1235
AR5K_XRMODE_FRAME_HOLD_MAR5K_XRMODE_FRAME_HOLD_M 0xfff00000 reg.h Mask for frame hold (?)
1236
AR5K_XRMODE_FRAME_HOLD_SAR5K_XRMODE_FRAME_HOLD_S 20 reg.h  
1237
AR5K_XRDELAYAR5K_XRDELAY 0x80c4 reg.h Register Address
1238
AR5K_XRDELAY_SLOT_DELAY_MAR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff reg.h Mask for slot delay
1239
AR5K_XRDELAY_SLOT_DELAY_SAR5K_XRDELAY_SLOT_DELAY_S 0 reg.h  
1240
AR5K_XRDELAY_CHIRP_DELAY_MAR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 reg.h Mask for CHIRP data delay
1241
AR5K_XRDELAY_CHIRP_DELAY_SAR5K_XRDELAY_CHIRP_DELAY_S 16 reg.h  
1242
AR5K_XRTIMEOUTAR5K_XRTIMEOUT 0x80c8 reg.h Register Address
1243
AR5K_XRTIMEOUT_CHIRP_MAR5K_XRTIMEOUT_CHIRP_M 0x0000ffff reg.h Mask for CHIRP timeout
1244
AR5K_XRTIMEOUT_CHIRP_SAR5K_XRTIMEOUT_CHIRP_S 0 reg.h  
1245
AR5K_XRTIMEOUT_POLL_MAR5K_XRTIMEOUT_POLL_M 0xffff0000 reg.h Mask for Poll timeout
1246
AR5K_XRTIMEOUT_POLL_SAR5K_XRTIMEOUT_POLL_S 16 reg.h  
1247
AR5K_XRCHIRPAR5K_XRCHIRP 0x80cc reg.h Register Address
1248
AR5K_XRCHIRP_SENDAR5K_XRCHIRP_SEND 0x00000001 reg.h Send CHIRP
1249
AR5K_XRCHIRP_GAPAR5K_XRCHIRP_GAP 0xffff0000 reg.h Mask for CHIRP gap (?)
1250
AR5K_XRSTOMPAR5K_XRSTOMP 0x80d0 reg.h Register Address
1251
AR5K_XRSTOMP_TXAR5K_XRSTOMP_TX 0x00000001 reg.h Stomp Tx (?)
1252
AR5K_XRSTOMP_RXAR5K_XRSTOMP_RX 0x00000002 reg.h Stomp Rx (?)
1253
AR5K_XRSTOMP_TX_RSSIAR5K_XRSTOMP_TX_RSSI 0x00000004 reg.h Stomp Tx RSSI (?)
1254
AR5K_XRSTOMP_TX_BSSIDAR5K_XRSTOMP_TX_BSSID 0x00000008 reg.h Stomp Tx BSSID (?)
1255
AR5K_XRSTOMP_DATAAR5K_XRSTOMP_DATA 0x00000010 reg.h Stomp data (?)
1256
AR5K_XRSTOMP_RSSI_THRESAR5K_XRSTOMP_RSSI_THRES 0x0000ff00 reg.h Mask for XR RSSI threshold
1257
AR5K_SLEEP0AR5K_SLEEP0 0x80d4 reg.h Register Address
1258
AR5K_SLEEP0_NEXT_DTIMAR5K_SLEEP0_NEXT_DTIM 0x0007ffff reg.h Mask for next DTIM (?)
1259
AR5K_SLEEP0_NEXT_DTIM_SAR5K_SLEEP0_NEXT_DTIM_S 0 reg.h  
1260
AR5K_SLEEP0_ASSUME_DTIMAR5K_SLEEP0_ASSUME_DTIM 0x00080000 reg.h Assume DTIM
1261
AR5K_SLEEP0_ENH_SLEEP_ENAR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 reg.h Enable enchanced sleep control
1262
AR5K_SLEEP0_CABTOAR5K_SLEEP0_CABTO 0xff000000 reg.h Mask for CAB Time Out
1263
AR5K_SLEEP0_CABTO_SAR5K_SLEEP0_CABTO_S 24 reg.h  
1264
AR5K_SLEEP1AR5K_SLEEP1 0x80d8 reg.h Register Address
1265
AR5K_SLEEP1_NEXT_TIMAR5K_SLEEP1_NEXT_TIM 0x0007ffff reg.h Mask for next TIM (?)
1266
AR5K_SLEEP1_NEXT_TIM_SAR5K_SLEEP1_NEXT_TIM_S 0 reg.h  
1267
AR5K_SLEEP1_BEACON_TOAR5K_SLEEP1_BEACON_TO 0xff000000 reg.h Mask for Beacon Time Out
1268
AR5K_SLEEP1_BEACON_TO_SAR5K_SLEEP1_BEACON_TO_S 24 reg.h  
1269
AR5K_SLEEP2AR5K_SLEEP2 0x80dc reg.h Register Address
1270
AR5K_SLEEP2_TIM_PERAR5K_SLEEP2_TIM_PER 0x0000ffff reg.h Mask for TIM period (?)
1271
AR5K_SLEEP2_TIM_PER_SAR5K_SLEEP2_TIM_PER_S 0 reg.h  
1272
AR5K_SLEEP2_DTIM_PERAR5K_SLEEP2_DTIM_PER 0xffff0000 reg.h Mask for DTIM period (?)
1273
AR5K_SLEEP2_DTIM_PER_SAR5K_SLEEP2_DTIM_PER_S 16 reg.h  
1274
AR5K_BSS_IDM0AR5K_BSS_IDM0 0x80e0 reg.h Upper bits
1275
AR5K_BSS_IDM1AR5K_BSS_IDM1 0x80e4 reg.h Lower bits
1276
AR5K_TXPCAR5K_TXPC 0x80e8 reg.h Register Address
1277
AR5K_TXPC_ACK_MAR5K_TXPC_ACK_M 0x0000003f reg.h ACK tx power
1278
AR5K_TXPC_ACK_SAR5K_TXPC_ACK_S 0 reg.h  
1279
AR5K_TXPC_CTS_MAR5K_TXPC_CTS_M 0x00003f00 reg.h CTS tx power
1280
AR5K_TXPC_CTS_SAR5K_TXPC_CTS_S 8 reg.h  
1281
AR5K_TXPC_CHIRP_MAR5K_TXPC_CHIRP_M 0x003f0000 reg.h CHIRP tx power
1282
AR5K_TXPC_CHIRP_SAR5K_TXPC_CHIRP_S 16 reg.h  
1283
AR5K_TXPC_DOPPLERAR5K_TXPC_DOPPLER 0x0f000000 reg.h Doppler chirp span (?)
1284
AR5K_TXPC_DOPPLER_SAR5K_TXPC_DOPPLER_S 24 reg.h  
1285
AR5K_PROFCNT_TXAR5K_PROFCNT_TX 0x80ec reg.h Tx count
1286
AR5K_PROFCNT_RXAR5K_PROFCNT_RX 0x80f0 reg.h Rx count
1287
AR5K_PROFCNT_RXCLRAR5K_PROFCNT_RXCLR 0x80f4 reg.h Clear Rx count
1288
AR5K_PROFCNT_CYCLEAR5K_PROFCNT_CYCLE 0x80f8 reg.h Cycle count (?)
1289
AR5K_QUIET_CTL1AR5K_QUIET_CTL1 0x80fc reg.h Register Address
1290
AR5K_QUIET_CTL1_NEXT_QT_TSFAR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff reg.h Next quiet period TSF (TU)
1291
AR5K_QUIET_CTL1_NEXT_QT_TSF_SAR5K_QUIET_CTL1_NEXT_QT_TSF_S 0 reg.h  
1292
AR5K_QUIET_CTL1_QT_ENAR5K_QUIET_CTL1_QT_EN 0x00010000 reg.h Enable quiet period
1293
AR5K_QUIET_CTL1_ACK_CTS_ENAR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 reg.h Send ACK/CTS during quiet period
1294
AR5K_QUIET_CTL2AR5K_QUIET_CTL2 0x8100 reg.h Register Address
1295
AR5K_QUIET_CTL2_QT_PERAR5K_QUIET_CTL2_QT_PER 0x0000ffff reg.h Mask for quiet period periodicity
1296
AR5K_QUIET_CTL2_QT_PER_SAR5K_QUIET_CTL2_QT_PER_S 0 reg.h  
1297
AR5K_QUIET_CTL2_QT_DURAR5K_QUIET_CTL2_QT_DUR 0xffff0000 reg.h Mask for quiet period duration
1298
AR5K_QUIET_CTL2_QT_DUR_SAR5K_QUIET_CTL2_QT_DUR_S 16 reg.h  
1299
AR5K_TSF_PARMAR5K_TSF_PARM 0x8104 reg.h Register Address
1300
AR5K_TSF_PARM_INCAR5K_TSF_PARM_INC 0x000000ff reg.h Mask for TSF increment
1301
AR5K_TSF_PARM_INC_SAR5K_TSF_PARM_INC_S 0 reg.h  
1302
AR5K_QOS_NOACKAR5K_QOS_NOACK 0x8108 reg.h Register Address
1303
AR5K_QOS_NOACK_2BIT_VALUESAR5K_QOS_NOACK_2BIT_VALUES 0x0000000f reg.h ???
1304
AR5K_QOS_NOACK_2BIT_VALUES_SAR5K_QOS_NOACK_2BIT_VALUES_S 0 reg.h  
1305
AR5K_QOS_NOACK_BIT_OFFSETAR5K_QOS_NOACK_BIT_OFFSET 0x00000070 reg.h ???
1306
AR5K_QOS_NOACK_BIT_OFFSET_SAR5K_QOS_NOACK_BIT_OFFSET_S 4 reg.h  
1307
AR5K_QOS_NOACK_BYTE_OFFSETAR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 reg.h ???
1308
AR5K_QOS_NOACK_BYTE_OFFSET_SAR5K_QOS_NOACK_BYTE_OFFSET_S 7 reg.h  
1309
AR5K_PHY_ERR_FILAR5K_PHY_ERR_FIL 0x810c reg.h  
1310
AR5K_PHY_ERR_FIL_RADARAR5K_PHY_ERR_FIL_RADAR 0x00000020 reg.h Radar signal
1311
AR5K_PHY_ERR_FIL_OFDMAR5K_PHY_ERR_FIL_OFDM 0x00020000 reg.h OFDM false detect (ANI)
1312
AR5K_PHY_ERR_FIL_CCKAR5K_PHY_ERR_FIL_CCK 0x02000000 reg.h CCK false detect (ANI)
1313
AR5K_XRLAT_TXAR5K_XRLAT_TX 0x8110 reg.h  
1314
AR5K_ACKSIFSAR5K_ACKSIFS 0x8114 reg.h Register Address
1315
AR5K_ACKSIFS_INCAR5K_ACKSIFS_INC 0x00000000 reg.h ACK SIFS Increment (field)
1316
AR5K_MIC_QOS_CTLAR5K_MIC_QOS_CTL 0x8118 reg.h Register Address
1317
AR5K_MIC_QOS_CTL_MQ_ENAR5K_MIC_QOS_CTL_MQ_EN 0x00010000 reg.h Enable MIC QoS
1318
AR5K_MIC_QOS_SELAR5K_MIC_QOS_SEL 0x811c reg.h  
1319
AR5K_MISC_MODEAR5K_MISC_MODE 0x8120 reg.h Register Address
1320
AR5K_MISC_MODE_FBSSID_MATCHAR5K_MISC_MODE_FBSSID_MATCH 0x00000001 reg.h Force BSSID match
1321
AR5K_MISC_MODE_ACKSIFS_MEMAR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 reg.h ACK SIFS memory (?)
1322
AR5K_MISC_MODE_COMBINED_MICAR5K_MISC_MODE_COMBINED_MIC 0x00000004 reg.h use rx/tx MIC key
1323
AR5K_OFDM_FIL_CNTAR5K_OFDM_FIL_CNT 0x8124 reg.h  
1324
AR5K_CCK_FIL_CNTAR5K_CCK_FIL_CNT 0x8128 reg.h  
1325
AR5K_PHYERR_CNT1AR5K_PHYERR_CNT1 0x812c reg.h  
1326
AR5K_PHYERR_CNT1_MASKAR5K_PHYERR_CNT1_MASK 0x8130 reg.h  
1327
AR5K_PHYERR_CNT2AR5K_PHYERR_CNT2 0x8134 reg.h  
1328
AR5K_PHYERR_CNT2_MASKAR5K_PHYERR_CNT2_MASK 0x8138 reg.h  
1329
AR5K_TSF_THRESAR5K_TSF_THRES 0x813c reg.h  
1330
AR5K_RATE_ACKSIFS_BASEAR5K_RATE_ACKSIFS_BASE 0x8680 reg.h Register Address
1331
AR5K_RATE_ACKSIFS_NORMALAR5K_RATE_ACKSIFS_NORMAL 0x00000001 reg.h Normal SIFS (field)
1332
AR5K_RATE_ACKSIFS_TURBOAR5K_RATE_ACKSIFS_TURBO 0x00000400 reg.h Turbo SIFS (field)
1333
AR5K_RATE_DUR_BASEAR5K_RATE_DUR_BASE 0x8700 reg.h  
1334
AR5K_RATE2DB_BASEAR5K_RATE2DB_BASE 0x87c0 reg.h  
1335
AR5K_DB2RATE_BASEAR5K_DB2RATE_BASE 0x87e0 reg.h  
1336
AR5K_KEYTABLE_0_5210AR5K_KEYTABLE_0_5210 0x9000 reg.h  
1337
AR5K_KEYTABLE_0_5211AR5K_KEYTABLE_0_5211 0x8800 reg.h  
1338
AR5K_KEYTABLE_TYPE_40AR5K_KEYTABLE_TYPE_40 0x00000000 reg.h  
1339
AR5K_KEYTABLE_TYPE_104AR5K_KEYTABLE_TYPE_104 0x00000001 reg.h  
1340
AR5K_KEYTABLE_TYPE_128AR5K_KEYTABLE_TYPE_128 0x00000003 reg.h  
1341
AR5K_KEYTABLE_TYPE_TKIPAR5K_KEYTABLE_TYPE_TKIP 0x00000004 reg.h [5212+]
1342
AR5K_KEYTABLE_TYPE_AESAR5K_KEYTABLE_TYPE_AES 0x00000005 reg.h [5211+]
1343
AR5K_KEYTABLE_TYPE_CCMAR5K_KEYTABLE_TYPE_CCM 0x00000006 reg.h [5212+]
1344
AR5K_KEYTABLE_TYPE_NULLAR5K_KEYTABLE_TYPE_NULL 0x00000007 reg.h [5211+]
1345
AR5K_KEYTABLE_ANTENNAAR5K_KEYTABLE_ANTENNA 0x00000008 reg.h [5212+]
1346
AR5K_KEYTABLE_VALIDAR5K_KEYTABLE_VALID 0x00008000 reg.h  
1347
AR5K_KEYTABLE_MIC_OFFSETAR5K_KEYTABLE_MIC_OFFSET 64 reg.h  
1348
AR5K_KEYTABLE_SIZE_5210AR5K_KEYTABLE_SIZE_5210 64 reg.h  
1349
AR5K_KEYTABLE_SIZE_5211AR5K_KEYTABLE_SIZE_5211 128 reg.h  
1350
AR5K_KEYTABLE_SIZEAR5K_KEYTABLE_SIZE (ah->ah_version == AR5K_AR5210 ? \ AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) reg.h  
1351
AR5K_PHY_BASEAR5K_PHY_BASE 0x9800 reg.h  
1352
AR5K_PHY_TST2AR5K_PHY_TST2 0x9800 reg.h Register Address
1353
AR5K_PHY_TST2_TRIG_SELAR5K_PHY_TST2_TRIG_SEL 0x00000007 reg.h Trigger select (?)
1354
AR5K_PHY_TST2_TRIGAR5K_PHY_TST2_TRIG 0x00000010 reg.h Trigger (?)
1355
AR5K_PHY_TST2_CBUS_MODEAR5K_PHY_TST2_CBUS_MODE 0x00000060 reg.h Cardbus mode (?)
1356
AR5K_PHY_TST2_CLK32AR5K_PHY_TST2_CLK32 0x00000400 reg.h CLK_OUT is CLK32 (32Khz external)
1357
AR5K_PHY_TST2_CHANCOR_DUMP_ENAR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 reg.h Enable Chancor dump (?)
1358
AR5K_PHY_TST2_EVEN_CHANCOR_DUMPAR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 reg.h Even Chancor dump (?)
1359
AR5K_PHY_TST2_RFSILENT_ENAR5K_PHY_TST2_RFSILENT_EN 0x00002000 reg.h Enable RFSILENT
1360
AR5K_PHY_TST2_ALT_RFDATAAR5K_PHY_TST2_ALT_RFDATA 0x00004000 reg.h Alternate RFDATA (5-2GHz switch ?)
1361
AR5K_PHY_TST2_MINI_OBS_ENAR5K_PHY_TST2_MINI_OBS_EN 0x00008000 reg.h Enable mini OBS (?)
1362
AR5K_PHY_TST2_RX2_IS_RX5_INVAR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 reg.h 2GHz rx path is the 5GHz path inverted (?)
1363
AR5K_PHY_TST2_SLOW_CLK160AR5K_PHY_TST2_SLOW_CLK160 0x00020000 reg.h Slow CLK160 (?)
1364
AR5K_PHY_TST2_AGC_OBS_SEL_3AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 reg.h AGC OBS Select 3 (?)
1365
AR5K_PHY_TST2_BBB_OBS_SELAR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 reg.h BB OBS Select (field ?)
1366
AR5K_PHY_TST2_ADC_OBS_SELAR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 reg.h ADC OBS Select (field ?)
1367
AR5K_PHY_TST2_RX_CLR_SELAR5K_PHY_TST2_RX_CLR_SEL 0x08000000 reg.h RX Clear Select (?)
1368
AR5K_PHY_TST2_FORCE_AGC_CLRAR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 reg.h Force AGC clear (?)
1369
AR5K_PHY_SHIFT_2GHZAR5K_PHY_SHIFT_2GHZ 0x00004007 reg.h Used to access 2GHz radios
1370
AR5K_PHY_SHIFT_5GHZAR5K_PHY_SHIFT_5GHZ 0x00000007 reg.h Used to access 5GHz radios (default)
1371
AR5K_PHY_TURBOAR5K_PHY_TURBO 0x9804 reg.h Register Address
1372
AR5K_PHY_TURBO_MODEAR5K_PHY_TURBO_MODE 0x00000001 reg.h Enable turbo mode
1373
AR5K_PHY_TURBO_SHORTAR5K_PHY_TURBO_SHORT 0x00000002 reg.h Set short symbols to turbo mode
1374
AR5K_PHY_TURBO_MIMOAR5K_PHY_TURBO_MIMO 0x00000004 reg.h Set turbo for mimo mimo
1375
AR5K_PHY_AGCAR5K_PHY_AGC 0x9808 reg.h Register Address
1376
AR5K_PHY_TST1AR5K_PHY_TST1 0x9808 reg.h  
1377
AR5K_PHY_AGC_DISABLEAR5K_PHY_AGC_DISABLE 0x08000000 reg.h Disable AGC to A2 (?)
1378
AR5K_PHY_TST1_TXHOLDAR5K_PHY_TST1_TXHOLD 0x00003800 reg.h Set tx hold (?)
1379
AR5K_PHY_TST1_TXSRC_SRCAR5K_PHY_TST1_TXSRC_SRC 0x00000002 reg.h Used with bit 7 (?)
1380
AR5K_PHY_TST1_TXSRC_SRC_SAR5K_PHY_TST1_TXSRC_SRC_S 1 reg.h  
1381
AR5K_PHY_TST1_TXSRC_ALTAR5K_PHY_TST1_TXSRC_ALT 0x00000080 reg.h Set input to tsdac (?)
1382
AR5K_PHY_TST1_TXSRC_ALT_SAR5K_PHY_TST1_TXSRC_ALT_S 7 reg.h  
1383
AR5K_PHY_TIMING_3AR5K_PHY_TIMING_3 0x9814 reg.h  
1384
AR5K_PHY_TIMING_3_DSC_MANAR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 reg.h  
1385
AR5K_PHY_TIMING_3_DSC_MAN_SAR5K_PHY_TIMING_3_DSC_MAN_S 17 reg.h  
1386
AR5K_PHY_TIMING_3_DSC_EXPAR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 reg.h  
1387
AR5K_PHY_TIMING_3_DSC_EXP_SAR5K_PHY_TIMING_3_DSC_EXP_S 13 reg.h  
1388
AR5K_PHY_CHIP_IDAR5K_PHY_CHIP_ID 0x9818 reg.h  
1389
AR5K_PHY_ACTAR5K_PHY_ACT 0x981c reg.h Register Address
1390
AR5K_PHY_ACT_ENABLEAR5K_PHY_ACT_ENABLE 0x00000001 reg.h Activate PHY
1391
AR5K_PHY_ACT_DISABLEAR5K_PHY_ACT_DISABLE 0x00000002 reg.h Deactivate PHY
1392
AR5K_PHY_RF_CTL2AR5K_PHY_RF_CTL2 0x9824 reg.h Register Address
1393
AR5K_PHY_RF_CTL2_TXF2TXD_STARTAR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f reg.h TX frame to TX data start
1394
AR5K_PHY_RF_CTL2_TXF2TXD_START_AR5K_PHY_RF_CTL2_TXF2TXD_START_ 0 reg.h  
1395
AR5K_PHY_RF_CTL3AR5K_PHY_RF_CTL3 0x9828 reg.h Register Address
1396
AR5K_PHY_RF_CTL3_TXE2XLNA_ONAR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 reg.h TX end to XLNA on
1397
AR5K_PHY_RF_CTL3_TXE2XLNA_ON_SAR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8 reg.h  
1398
AR5K_PHY_ADC_CTLAR5K_PHY_ADC_CTL 0x982c reg.h  
1399
AR5K_PHY_ADC_CTL_INBUFGAIN_OFFAR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003 reg.h  
1400
AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_ 0 reg.h  
1401
AR5K_PHY_ADC_CTL_PWD_DAC_OFFAR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000 reg.h  
1402
AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OAR5K_PHY_ADC_CTL_PWD_BAND_GAP_O 0x00004000 reg.h  
1403
AR5K_PHY_ADC_CTL_PWD_ADC_OFFAR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000 reg.h  
1404
AR5K_PHY_ADC_CTL_INBUFGAIN_ONAR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000 reg.h  
1405
AR5K_PHY_ADC_CTL_INBUFGAIN_ON_SAR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16 reg.h  
1406
AR5K_PHY_RF_CTL4AR5K_PHY_RF_CTL4 0x9834 reg.h Register Address
1407
AR5K_PHY_RF_CTL4_TXF2XPA_A_ONAR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 reg.h TX frame to XPA A on (field)
1408
AR5K_PHY_RF_CTL4_TXF2XPA_B_ONAR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 reg.h TX frame to XPA B on (field)
1409
AR5K_PHY_RF_CTL4_TXE2XPA_A_OFFAR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 reg.h TX end to XPA A off (field)
1410
AR5K_PHY_RF_CTL4_TXE2XPA_B_OFFAR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 reg.h TX end to XPA B off (field)
1411
AR5K_PHY_PA_CTLAR5K_PHY_PA_CTL 0x9838 reg.h Register Address
1412
AR5K_PHY_PA_CTL_XPA_A_HIAR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 reg.h XPA A high (?)
1413
AR5K_PHY_PA_CTL_XPA_B_HIAR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 reg.h XPA B high (?)
1414
AR5K_PHY_PA_CTL_XPA_A_ENAR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 reg.h Enable XPA A
1415
AR5K_PHY_PA_CTL_XPA_B_ENAR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 reg.h Enable XPA B
1416
AR5K_PHY_SETTLINGAR5K_PHY_SETTLING 0x9844 reg.h Register Address
1417
AR5K_PHY_SETTLING_AGCAR5K_PHY_SETTLING_AGC 0x0000007f reg.h AGC settling time
1418
AR5K_PHY_SETTLING_AGC_SAR5K_PHY_SETTLING_AGC_S 0 reg.h  
1419
AR5K_PHY_SETTLING_SWITCHAR5K_PHY_SETTLING_SWITCH 0x00003f80 reg.h Switch settlig time
1420
AR5K_PHY_SETTLING_SWITCH_SAR5K_PHY_SETTLING_SWITCH_S 7 reg.h  
1421
AR5K_PHY_GAINAR5K_PHY_GAIN 0x9848 reg.h Register Address
1422
AR5K_PHY_GAIN_TXRX_ATTENAR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 reg.h TX-RX Attenuation
1423
AR5K_PHY_GAIN_TXRX_ATTEN_SAR5K_PHY_GAIN_TXRX_ATTEN_S 12 reg.h  
1424
AR5K_PHY_GAIN_TXRX_RF_MAXAR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000 reg.h  
1425
AR5K_PHY_GAIN_TXRX_RF_MAX_SAR5K_PHY_GAIN_TXRX_RF_MAX_S 18 reg.h  
1426
AR5K_PHY_GAIN_OFFSETAR5K_PHY_GAIN_OFFSET 0x984c reg.h Register Address
1427
AR5K_PHY_GAIN_OFFSET_RXTX_FLAGAR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 reg.h RX-TX flag (?)
1428
AR5K_PHY_DESIRED_SIZEAR5K_PHY_DESIRED_SIZE 0x9850 reg.h Register Address
1429
AR5K_PHY_DESIRED_SIZE_ADCAR5K_PHY_DESIRED_SIZE_ADC 0x000000ff reg.h ADC desired size
1430
AR5K_PHY_DESIRED_SIZE_ADC_SAR5K_PHY_DESIRED_SIZE_ADC_S 0 reg.h  
1431
AR5K_PHY_DESIRED_SIZE_PGAAR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 reg.h PGA desired size
1432
AR5K_PHY_DESIRED_SIZE_PGA_SAR5K_PHY_DESIRED_SIZE_PGA_S 8 reg.h  
1433
AR5K_PHY_DESIRED_SIZE_TOTAR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 reg.h Total desired size
1434
AR5K_PHY_DESIRED_SIZE_TOT_SAR5K_PHY_DESIRED_SIZE_TOT_S 20 reg.h  
1435
AR5K_PHY_SIGAR5K_PHY_SIG 0x9858 reg.h Register Address
1436
AR5K_PHY_SIG_FIRSTEPAR5K_PHY_SIG_FIRSTEP 0x0003f000 reg.h FIRSTEP
1437
AR5K_PHY_SIG_FIRSTEP_SAR5K_PHY_SIG_FIRSTEP_S 12 reg.h  
1438
AR5K_PHY_SIG_FIRPWRAR5K_PHY_SIG_FIRPWR 0x03fc0000 reg.h FIPWR
1439
AR5K_PHY_SIG_FIRPWR_SAR5K_PHY_SIG_FIRPWR_S 18 reg.h  
1440
AR5K_PHY_AGCCOARSEAR5K_PHY_AGCCOARSE 0x985c reg.h Register Address
1441
AR5K_PHY_AGCCOARSE_LOAR5K_PHY_AGCCOARSE_LO 0x00007f80 reg.h AGC Coarse low
1442
AR5K_PHY_AGCCOARSE_LO_SAR5K_PHY_AGCCOARSE_LO_S 7 reg.h  
1443
AR5K_PHY_AGCCOARSE_HIAR5K_PHY_AGCCOARSE_HI 0x003f8000 reg.h AGC Coarse high
1444
AR5K_PHY_AGCCOARSE_HI_SAR5K_PHY_AGCCOARSE_HI_S 15 reg.h  
1445
AR5K_PHY_AGCCTLAR5K_PHY_AGCCTL 0x9860 reg.h Register address
1446
AR5K_PHY_AGCCTL_CALAR5K_PHY_AGCCTL_CAL 0x00000001 reg.h Enable PHY calibration
1447
AR5K_PHY_AGCCTL_NFAR5K_PHY_AGCCTL_NF 0x00000002 reg.h Enable Noise Floor calibration
1448
AR5K_PHY_AGCCTL_NF_ENAR5K_PHY_AGCCTL_NF_EN 0x00008000 reg.h Enable nf calibration to happen (?)
1449
AR5K_PHY_AGCCTL_NF_NOUPDATEAR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 reg.h Don't update nf automaticaly
1450
AR5K_PHY_NFAR5K_PHY_NF 0x9864 reg.h Register address
1451
AR5K_PHY_NF_MAR5K_PHY_NF_M 0x000001ff reg.h Noise floor mask
1452
AR5K_PHY_NF_ACTIVEAR5K_PHY_NF_ACTIVE 0x00000100 reg.h Noise floor calibration still active
1453
AR5K_PHY_NF_THRESH62AR5K_PHY_NF_THRESH62 0x0007f000 reg.h Thresh62 -check ANI patent- (field)
1454
AR5K_PHY_NF_THRESH62_SAR5K_PHY_NF_THRESH62_S 12 reg.h  
1455
AR5K_PHY_NF_MINCCA_PWRAR5K_PHY_NF_MINCCA_PWR 0x0ff80000 reg.h ???
1456
AR5K_PHY_NF_MINCCA_PWR_SAR5K_PHY_NF_MINCCA_PWR_S 19 reg.h  
1457
AR5K_PHY_ADCSATAR5K_PHY_ADCSAT 0x9868 reg.h  
1458
AR5K_PHY_ADCSAT_ICNTAR5K_PHY_ADCSAT_ICNT 0x0001f800 reg.h  
1459
AR5K_PHY_ADCSAT_ICNT_SAR5K_PHY_ADCSAT_ICNT_S 11 reg.h  
1460
AR5K_PHY_ADCSAT_THRAR5K_PHY_ADCSAT_THR 0x000007e0 reg.h  
1461
AR5K_PHY_ADCSAT_THR_SAR5K_PHY_ADCSAT_THR_S 5 reg.h  
1462
AR5K_PHY_WEAK_OFDM_HIGH_THRAR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868 reg.h  
1463
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ 0x0000001f reg.h  
1464
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ 0 reg.h  
1465
AR5K_PHY_WEAK_OFDM_HIGH_THR_M1AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000 reg.h  
1466
AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_ 17 reg.h  
1467
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000 reg.h  
1468
AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ 24 reg.h  
1469
AR5K_PHY_WEAK_OFDM_LOW_THRAR5K_PHY_WEAK_OFDM_LOW_THR 0x986c reg.h  
1470
AR5K_PHY_WEAK_OFDM_LOW_THR_SELFAR5K_PHY_WEAK_OFDM_LOW_THR_SELF 0x00000001 reg.h  
1471
AR5K_PHY_WEAK_OFDM_LOW_THR_M2_CAR5K_PHY_WEAK_OFDM_LOW_THR_M2_C 0x00003f00 reg.h  
1472
AR5K_PHY_WEAK_OFDM_LOW_THR_M2_CAR5K_PHY_WEAK_OFDM_LOW_THR_M2_C 8 reg.h  
1473
AR5K_PHY_WEAK_OFDM_LOW_THR_M1AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000 reg.h  
1474
AR5K_PHY_WEAK_OFDM_LOW_THR_M1_SAR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14 reg.h  
1475
AR5K_PHY_WEAK_OFDM_LOW_THR_M2AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000 reg.h  
1476
AR5K_PHY_WEAK_OFDM_LOW_THR_M2_SAR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21 reg.h  
1477
AR5K_PHY_SCRAR5K_PHY_SCR 0x9870 reg.h  
1478
AR5K_PHY_SLMTAR5K_PHY_SLMT 0x9874 reg.h  
1479
AR5K_PHY_SLMT_32MHZAR5K_PHY_SLMT_32MHZ 0x0000007f reg.h  
1480
AR5K_PHY_SCALAR5K_PHY_SCAL 0x9878 reg.h  
1481
AR5K_PHY_SCAL_32MHZAR5K_PHY_SCAL_32MHZ 0x0000000e reg.h  
1482
AR5K_PHY_SCAL_32MHZ_2417AR5K_PHY_SCAL_32MHZ_2417 0x0000000a reg.h  
1483
AR5K_PHY_SCAL_32MHZ_HB63AR5K_PHY_SCAL_32MHZ_HB63 0x00000032 reg.h  
1484
AR5K_PHY_PLLAR5K_PHY_PLL 0x987c reg.h  
1485
AR5K_PHY_PLL_20MHZAR5K_PHY_PLL_20MHZ 0x00000013 reg.h For half rate (?)
1486
AR5K_PHY_PLL_40MHZ_5211AR5K_PHY_PLL_40MHZ_5211 0x00000018 reg.h  
1487
AR5K_PHY_PLL_40MHZ_5212AR5K_PHY_PLL_40MHZ_5212 0x000000aa reg.h  
1488
AR5K_PHY_PLL_40MHZ_5413AR5K_PHY_PLL_40MHZ_5413 0x00000004 reg.h  
1489
AR5K_PHY_PLL_40MHZAR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \ AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) reg.h  
1490
AR5K_PHY_PLL_44MHZ_5211AR5K_PHY_PLL_44MHZ_5211 0x00000019 reg.h  
1491
AR5K_PHY_PLL_44MHZ_5212AR5K_PHY_PLL_44MHZ_5212 0x000000ab reg.h  
1492
AR5K_PHY_PLL_44MHZAR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \ AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) reg.h  
1493
AR5K_PHY_PLL_RF5111AR5K_PHY_PLL_RF5111 0x00000000 reg.h  
1494
AR5K_PHY_PLL_RF5112AR5K_PHY_PLL_RF5112 0x00000040 reg.h  
1495
AR5K_PHY_PLL_HALF_RATEAR5K_PHY_PLL_HALF_RATE 0x00000100 reg.h  
1496
AR5K_PHY_PLL_QUARTER_RATEAR5K_PHY_PLL_QUARTER_RATE 0x00000200 reg.h  
1497
AR5K_RF_BUFFERAR5K_RF_BUFFER 0x989c reg.h  
1498
AR5K_RF_BUFFER_CONTROL_0AR5K_RF_BUFFER_CONTROL_0 0x98c0 reg.h Channel on 5110
1499
AR5K_RF_BUFFER_CONTROL_1AR5K_RF_BUFFER_CONTROL_1 0x98c4 reg.h Bank 7 on 5112
1500
AR5K_RF_BUFFER_CONTROL_2AR5K_RF_BUFFER_CONTROL_2 0x98cc reg.h Bank 7 on 5111
1501
AR5K_RF_BUFFER_CONTROL_3AR5K_RF_BUFFER_CONTROL_3 0x98d0 reg.h Bank 2 on 5112
1502
AR5K_RF_BUFFER_CONTROL_4AR5K_RF_BUFFER_CONTROL_4 0x98d4 reg.h RF Stage register on 5110
1503
AR5K_RF_BUFFER_CONTROL_5AR5K_RF_BUFFER_CONTROL_5 0x98d8 reg.h Bank 3 on 5111
1504
AR5K_RF_BUFFER_CONTROL_6AR5K_RF_BUFFER_CONTROL_6 0x98dc reg.h Bank 3 on 5112
1505
AR5K_PHY_RFSTGAR5K_PHY_RFSTG 0x98d4 reg.h  
1506
AR5K_PHY_RFSTG_DISABLEAR5K_PHY_RFSTG_DISABLE 0x00000021 reg.h  
1507
AR5K_PHY_BIN_MASK_1AR5K_PHY_BIN_MASK_1 0x9900 reg.h  
1508
AR5K_PHY_BIN_MASK_2AR5K_PHY_BIN_MASK_2 0x9904 reg.h  
1509
AR5K_PHY_BIN_MASK_3AR5K_PHY_BIN_MASK_3 0x9908 reg.h  
1510
AR5K_PHY_BIN_MASK_CTLAR5K_PHY_BIN_MASK_CTL 0x990c reg.h  
1511
AR5K_PHY_BIN_MASK_CTL_MASK_4AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff reg.h  
1512
AR5K_PHY_BIN_MASK_CTL_MASK_4_SAR5K_PHY_BIN_MASK_CTL_MASK_4_S 0 reg.h  
1513
AR5K_PHY_BIN_MASK_CTL_RATEAR5K_PHY_BIN_MASK_CTL_RATE 0xff000000 reg.h  
1514
AR5K_PHY_BIN_MASK_CTL_RATE_SAR5K_PHY_BIN_MASK_CTL_RATE_S 24 reg.h  
1515
AR5K_PHY_ANT_CTLAR5K_PHY_ANT_CTL 0x9910 reg.h Register Address
1516
AR5K_PHY_ANT_CTL_TXRX_ENAR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 reg.h Enable TX/RX (?)
1517
AR5K_PHY_ANT_CTL_SECTORED_ANTAR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 reg.h Sectored Antenna
1518
AR5K_PHY_ANT_CTL_HITUNE5AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 reg.h Hitune5 (?)
1519
AR5K_PHY_ANT_CTL_SWTABLE_IDLEAR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 reg.h Switch table idle (?)
1520
AR5K_PHY_ANT_CTL_SWTABLE_IDLE_SAR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4 reg.h  
1521
AR5K_PHY_RX_DELAYAR5K_PHY_RX_DELAY 0x9914 reg.h Register Address
1522
AR5K_PHY_RX_DELAY_MAR5K_PHY_RX_DELAY_M 0x00003fff reg.h Mask for RX activate to receive delay (/100ns)
1523
AR5K_PHY_MAX_RX_LENAR5K_PHY_MAX_RX_LEN 0x991c reg.h  
1524
AR5K_PHY_IQAR5K_PHY_IQ 0x9920 reg.h Register Address
1525
AR5K_PHY_IQ_CORR_Q_Q_COFFAR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f reg.h Mask for q correction info
1526
AR5K_PHY_IQ_CORR_Q_I_COFFAR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 reg.h Mask for i correction info
1527
AR5K_PHY_IQ_CORR_Q_I_COFF_SAR5K_PHY_IQ_CORR_Q_I_COFF_S 5 reg.h  
1528
AR5K_PHY_IQ_CORR_ENABLEAR5K_PHY_IQ_CORR_ENABLE 0x00000800 reg.h Enable i/q correction
1529
AR5K_PHY_IQ_CAL_NUM_LOG_MAXAR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 reg.h Mask for max number of samples in log scale
1530
AR5K_PHY_IQ_CAL_NUM_LOG_MAX_SAR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 reg.h  
1531
AR5K_PHY_IQ_RUNAR5K_PHY_IQ_RUN 0x00010000 reg.h Run i/q calibration
1532
AR5K_PHY_IQ_USE_PT_DFAR5K_PHY_IQ_USE_PT_DF 0x00020000 reg.h Use pilot track df (?)
1533
AR5K_PHY_IQ_EARLY_TRIG_THRAR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 reg.h Early trigger threshold (?) (field)
1534
AR5K_PHY_IQ_PILOT_MASK_ENAR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 reg.h Enable pilot mask (?)
1535
AR5K_PHY_IQ_CHAN_MASK_ENAR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 reg.h Enable channel mask (?)
1536
AR5K_PHY_IQ_SPUR_FILT_ENAR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 reg.h Enable spur filter
1537
AR5K_PHY_IQ_SPUR_RSSI_ENAR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 reg.h Enable spur rssi
1538
AR5K_PHY_OFDM_SELFCORRAR5K_PHY_OFDM_SELFCORR 0x9924 reg.h Register Address
1539
AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 0x00000001 reg.h Enable cyclic RSSI thr 1
1540
AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 0x000000fe reg.h Mask for Cyclic RSSI threshold 1
1541
AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 1 reg.h  
1542
AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 0x00000100 reg.h Cyclic RSSI threshold 3 (field) (?)
1543
AR5K_PHY_OFDM_SELFCORR_RSSI_1ATAR5K_PHY_OFDM_SELFCORR_RSSI_1AT 0x00008000 reg.h Enable 1A RSSI threshold (?)
1544
AR5K_PHY_OFDM_SELFCORR_RSSI_1ATAR5K_PHY_OFDM_SELFCORR_RSSI_1AT 0x00010000 reg.h 1A RSSI threshold (field) (?)
1545
AR5K_PHY_OFDM_SELFCORR_LSCTHR_HAR5K_PHY_OFDM_SELFCORR_LSCTHR_H 0x00800000 reg.h Long sc threshold hi rssi (?)
1546
AR5K_PHY_WARM_RESETAR5K_PHY_WARM_RESET 0x9928 reg.h  
1547
AR5K_PHY_CTLAR5K_PHY_CTL 0x992c reg.h Register Address
1548
AR5K_PHY_CTL_RX_DRAIN_RATEAR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 reg.h RX drain rate (?)
1549
AR5K_PHY_CTL_LATE_TX_SIG_SYMAR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 reg.h Late tx signal symbol (?)
1550
AR5K_PHY_CTL_GEN_SCRAMBLERAR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 reg.h Generate scrambler
1551
AR5K_PHY_CTL_TX_ANT_SELAR5K_PHY_CTL_TX_ANT_SEL 0x00000008 reg.h TX antenna select
1552
AR5K_PHY_CTL_TX_ANT_STATICAR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 reg.h Static TX antenna
1553
AR5K_PHY_CTL_RX_ANT_SELAR5K_PHY_CTL_RX_ANT_SEL 0x00000020 reg.h RX antenna select
1554
AR5K_PHY_CTL_RX_ANT_STATICAR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 reg.h Static RX antenna
1555
AR5K_PHY_CTL_LOW_FREQ_SLE_ENAR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 reg.h Enable low freq sleep
1556
AR5K_PHY_PAPD_PROBEAR5K_PHY_PAPD_PROBE 0x9930 reg.h  
1557
AR5K_PHY_PAPD_PROBE_SH_HI_PARAR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001 reg.h  
1558
AR5K_PHY_PAPD_PROBE_PCDAC_BIASAR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002 reg.h  
1559
AR5K_PHY_PAPD_PROBE_COMP_GAINAR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040 reg.h  
1560
AR5K_PHY_PAPD_PROBE_TXPOWERAR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 reg.h  
1561
AR5K_PHY_PAPD_PROBE_TXPOWER_SAR5K_PHY_PAPD_PROBE_TXPOWER_S 9 reg.h  
1562
AR5K_PHY_PAPD_PROBE_TX_NEXTAR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 reg.h  
1563
AR5K_PHY_PAPD_PROBE_PREDIST_ENAR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000 reg.h  
1564
AR5K_PHY_PAPD_PROBE_TYPEAR5K_PHY_PAPD_PROBE_TYPE 0x01800000 reg.h [5112+]
1565
AR5K_PHY_PAPD_PROBE_TYPE_SAR5K_PHY_PAPD_PROBE_TYPE_S 23 reg.h  
1566
AR5K_PHY_PAPD_PROBE_TYPE_OFDMAR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 reg.h  
1567
AR5K_PHY_PAPD_PROBE_TYPE_XRAR5K_PHY_PAPD_PROBE_TYPE_XR 1 reg.h  
1568
AR5K_PHY_PAPD_PROBE_TYPE_CCKAR5K_PHY_PAPD_PROBE_TYPE_CCK 2 reg.h  
1569
AR5K_PHY_PAPD_PROBE_GAINFAR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 reg.h  
1570
AR5K_PHY_PAPD_PROBE_GAINF_SAR5K_PHY_PAPD_PROBE_GAINF_S 25 reg.h  
1571
AR5K_PHY_PAPD_PROBE_INI_5111AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 reg.h [5212+]
1572
AR5K_PHY_PAPD_PROBE_INI_5112AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 reg.h [5212+]
1573
AR5K_PHY_TXPOWER_RATE1AR5K_PHY_TXPOWER_RATE1 0x9934 reg.h  
1574
AR5K_PHY_TXPOWER_RATE2AR5K_PHY_TXPOWER_RATE2 0x9938 reg.h  
1575
AR5K_PHY_TXPOWER_RATE_MAXAR5K_PHY_TXPOWER_RATE_MAX 0x993c reg.h  
1576
AR5K_PHY_TXPOWER_RATE_MAX_TPC_EAR5K_PHY_TXPOWER_RATE_MAX_TPC_E 0x00000040 reg.h  
1577
AR5K_PHY_TXPOWER_RATE3AR5K_PHY_TXPOWER_RATE3 0xa234 reg.h  
1578
AR5K_PHY_TXPOWER_RATE4AR5K_PHY_TXPOWER_RATE4 0xa238 reg.h  
1579
AR5K_PHY_FRAME_CTL_5210AR5K_PHY_FRAME_CTL_5210 0x9804 reg.h  
1580
AR5K_PHY_FRAME_CTL_5211AR5K_PHY_FRAME_CTL_5211 0x9944 reg.h  
1581
AR5K_PHY_FRAME_CTLAR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) reg.h  
1582
AR5K_PHY_FRAME_CTL_TX_CLIPAR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 reg.h Mask for tx clip (?)
1583
AR5K_PHY_FRAME_CTL_TX_CLIP_SAR5K_PHY_FRAME_CTL_TX_CLIP_S 3 reg.h  
1584
AR5K_PHY_FRAME_CTL_PREP_CHINFOAR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 reg.h Prepend chan info
1585
AR5K_PHY_FRAME_CTL_EMUAR5K_PHY_FRAME_CTL_EMU 0x80000000 reg.h  
1586
AR5K_PHY_FRAME_CTL_EMU_SAR5K_PHY_FRAME_CTL_EMU_S 31 reg.h  
1587
AR5K_PHY_FRAME_CTL_TIMING_ERRAR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 reg.h PHY timing error
1588
AR5K_PHY_FRAME_CTL_PARITY_ERRAR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 reg.h Parity error
1589
AR5K_PHY_FRAME_CTL_ILLRATE_ERRAR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 reg.h Illegal rate
1590
AR5K_PHY_FRAME_CTL_ILLLEN_ERRAR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 reg.h Illegal length
1591
AR5K_PHY_FRAME_CTL_SERVICE_ERRAR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 reg.h  
1592
AR5K_PHY_FRAME_CTL_TXURN_ERRAR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 reg.h TX underrun
1593
AR5K_PHY_FRAME_CTL_INIAR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ AR5K_PHY_FRAME_CTL_TXURN_ERR | \ AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ AR5K_PHY_FRAME_CTL_ILLRAT reg.h  
1594
AR5K_PHY_TX_PWR_ADJAR5K_PHY_TX_PWR_ADJ 0x994c reg.h  
1595
AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DEAR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE 0x00000fc0 reg.h  
1596
AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DEAR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE 6 reg.h  
1597
AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_IAR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I 0x00fc0000 reg.h  
1598
AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_IAR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I 18 reg.h  
1599
AR5K_PHY_RADARAR5K_PHY_RADAR 0x9954 reg.h  
1600
AR5K_PHY_RADAR_ENABLEAR5K_PHY_RADAR_ENABLE 0x00000001 reg.h  
1601
AR5K_PHY_RADAR_DISABLEAR5K_PHY_RADAR_DISABLE 0x00000000 reg.h  
1602
AR5K_PHY_RADAR_INBANDTHRAR5K_PHY_RADAR_INBANDTHR 0x0000003e reg.h Inband threshold
1603
AR5K_PHY_RADAR_INBANDTHR_SAR5K_PHY_RADAR_INBANDTHR_S 1 reg.h  
1604
AR5K_PHY_RADAR_PRSSI_THRAR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 reg.h Pulse RSSI/SNR threshold
1605
AR5K_PHY_RADAR_PRSSI_THR_SAR5K_PHY_RADAR_PRSSI_THR_S 6 reg.h  
1606
AR5K_PHY_RADAR_PHEIGHT_THRAR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 reg.h Pulse height threshold
1607
AR5K_PHY_RADAR_PHEIGHT_THR_SAR5K_PHY_RADAR_PHEIGHT_THR_S 12 reg.h  
1608
AR5K_PHY_RADAR_RSSI_THRAR5K_PHY_RADAR_RSSI_THR 0x00fc0000 reg.h Radar RSSI/SNR threshold.
1609
AR5K_PHY_RADAR_RSSI_THR_SAR5K_PHY_RADAR_RSSI_THR_S 18 reg.h  
1610
AR5K_PHY_RADAR_FIRPWR_THRAR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 reg.h Finite Impulse Response
1611
AR5K_PHY_RADAR_FIRPWR_THRSAR5K_PHY_RADAR_FIRPWR_THRS 24 reg.h  
1612
AR5K_PHY_ANT_SWITCH_TABLE_0AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 reg.h  
1613
AR5K_PHY_ANT_SWITCH_TABLE_1AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 reg.h  
1614
AR5K_PHY_NFTHRESAR5K_PHY_NFTHRES 0x9968 reg.h  
1615
AR5K_PHY_SIGMA_DELTAAR5K_PHY_SIGMA_DELTA 0x996C reg.h  
1616
AR5K_PHY_SIGMA_DELTA_ADC_SELAR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 reg.h  
1617
AR5K_PHY_SIGMA_DELTA_ADC_SEL_SAR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0 reg.h  
1618
AR5K_PHY_SIGMA_DELTA_FILT2AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8 reg.h  
1619
AR5K_PHY_SIGMA_DELTA_FILT2_SAR5K_PHY_SIGMA_DELTA_FILT2_S 3 reg.h  
1620
AR5K_PHY_SIGMA_DELTA_FILT1AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00 reg.h  
1621
AR5K_PHY_SIGMA_DELTA_FILT1_SAR5K_PHY_SIGMA_DELTA_FILT1_S 8 reg.h  
1622
AR5K_PHY_SIGMA_DELTA_ADC_CLIPAR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000 reg.h  
1623
AR5K_PHY_SIGMA_DELTA_ADC_CLIP_SAR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13 reg.h  
1624
AR5K_PHY_RESTARTAR5K_PHY_RESTART 0x9970 reg.h restart
1625
AR5K_PHY_RESTART_DIV_GCAR5K_PHY_RESTART_DIV_GC 0x001c0000 reg.h Fast diversity gc_limit (?)
1626
AR5K_PHY_RESTART_DIV_GC_SAR5K_PHY_RESTART_DIV_GC_S 18 reg.h  
1627
AR5K_PHY_RFBUS_REQAR5K_PHY_RFBUS_REQ 0x997C reg.h  
1628
AR5K_PHY_RFBUS_REQ_REQUESTAR5K_PHY_RFBUS_REQ_REQUEST 0x00000001 reg.h  
1629
AR5K_PHY_TIMING_7AR5K_PHY_TIMING_7 0x9980 reg.h  
1630
AR5K_PHY_TIMING_8AR5K_PHY_TIMING_8 0x9984 reg.h  
1631
AR5K_PHY_TIMING_8_PILOT_MASK_2AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff reg.h  
1632
AR5K_PHY_TIMING_8_PILOT_MASK_2_AR5K_PHY_TIMING_8_PILOT_MASK_2_ 0 reg.h  
1633
AR5K_PHY_BIN_MASK2_1AR5K_PHY_BIN_MASK2_1 0x9988 reg.h  
1634
AR5K_PHY_BIN_MASK2_2AR5K_PHY_BIN_MASK2_2 0x998c reg.h  
1635
AR5K_PHY_BIN_MASK2_3AR5K_PHY_BIN_MASK2_3 0x9990 reg.h  
1636
AR5K_PHY_BIN_MASK2_4AR5K_PHY_BIN_MASK2_4 0x9994 reg.h  
1637
AR5K_PHY_BIN_MASK2_4_MASK_4AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff reg.h  
1638
AR5K_PHY_BIN_MASK2_4_MASK_4_SAR5K_PHY_BIN_MASK2_4_MASK_4_S 0 reg.h  
1639
AR5K_PHY_TIMING_9AR5K_PHY_TIMING_9 0x9998 reg.h  
1640
AR5K_PHY_TIMING_10AR5K_PHY_TIMING_10 0x999c reg.h  
1641
AR5K_PHY_TIMING_10_PILOT_MASK_2AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff reg.h  
1642
AR5K_PHY_TIMING_10_PILOT_MASK_2AR5K_PHY_TIMING_10_PILOT_MASK_2 0 reg.h  
1643
AR5K_PHY_TIMING_11AR5K_PHY_TIMING_11 0x99a0 reg.h Register address
1644
AR5K_PHY_TIMING_11_SPUR_DELTA_PAR5K_PHY_TIMING_11_SPUR_DELTA_P 0x000fffff reg.h Spur delta phase
1645
AR5K_PHY_TIMING_11_SPUR_DELTA_PAR5K_PHY_TIMING_11_SPUR_DELTA_P 0 reg.h  
1646
AR5K_PHY_TIMING_11_SPUR_FREQ_SDAR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 reg.h Freq sigma delta
1647
AR5K_PHY_TIMING_11_SPUR_FREQ_SDAR5K_PHY_TIMING_11_SPUR_FREQ_SD 20 reg.h  
1648
AR5K_PHY_TIMING_11_USE_SPUR_IN_AR5K_PHY_TIMING_11_USE_SPUR_IN_ 0x40000000 reg.h Spur filter in AGC detector
1649
AR5K_PHY_TIMING_11_USE_SPUR_IN_AR5K_PHY_TIMING_11_USE_SPUR_IN_ 0x80000000 reg.h Spur filter in OFDM self correlator
1650
AR5K_BB_GAIN_BASEAR5K_BB_GAIN_BASE 0x9b00 reg.h BaseBand Amplifier Gain table base address
1651
AR5K_RF_GAIN_BASEAR5K_RF_GAIN_BASE 0x9a00 reg.h RF Amplrifier Gain table base address
1652
AR5K_PHY_IQRES_CAL_PWR_IAR5K_PHY_IQRES_CAL_PWR_I 0x9c10 reg.h I (Inphase) power value
1653
AR5K_PHY_IQRES_CAL_PWR_QAR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 reg.h Q (Quadrature) power value
1654
AR5K_PHY_IQRES_CAL_CORRAR5K_PHY_IQRES_CAL_CORR 0x9c18 reg.h I/Q Correlation
1655
AR5K_PHY_CURRENT_RSSIAR5K_PHY_CURRENT_RSSI 0x9c1c reg.h  
1656
AR5K_PHY_RFBUS_GRANTAR5K_PHY_RFBUS_GRANT 0x9c20 reg.h  
1657
AR5K_PHY_RFBUS_GRANT_OKAR5K_PHY_RFBUS_GRANT_OK 0x00000001 reg.h  
1658
AR5K_PHY_ADC_TESTAR5K_PHY_ADC_TEST 0x9c24 reg.h  
1659
AR5K_PHY_ADC_TEST_IAR5K_PHY_ADC_TEST_I 0x00000001 reg.h  
1660
AR5K_PHY_ADC_TEST_QAR5K_PHY_ADC_TEST_Q 0x00000200 reg.h  
1661
AR5K_PHY_DAC_TESTAR5K_PHY_DAC_TEST 0x9c28 reg.h  
1662
AR5K_PHY_DAC_TEST_IAR5K_PHY_DAC_TEST_I 0x00000001 reg.h  
1663
AR5K_PHY_DAC_TEST_QAR5K_PHY_DAC_TEST_Q 0x00000200 reg.h  
1664
AR5K_PHY_PTATAR5K_PHY_PTAT 0x9c2c reg.h  
1665
AR5K_PHY_BAD_TX_RATEAR5K_PHY_BAD_TX_RATE 0x9c30 reg.h  
1666
AR5K_PHY_SPUR_PWRAR5K_PHY_SPUR_PWR 0x9c34 reg.h Register Address
1667
AR5K_PHY_SPUR_PWR_IAR5K_PHY_SPUR_PWR_I 0x00000001 reg.h SPUR Power estimate for I (field)
1668
AR5K_PHY_SPUR_PWR_QAR5K_PHY_SPUR_PWR_Q 0x00000100 reg.h SPUR Power estimate for Q (field)
1669
AR5K_PHY_SPUR_PWR_FILTAR5K_PHY_SPUR_PWR_FILT 0x00010000 reg.h Power with SPUR removed (field)
1670
AR5K_PHY_CHAN_STATUSAR5K_PHY_CHAN_STATUS 0x9c38 reg.h  
1671
AR5K_PHY_CHAN_STATUS_BT_ACTAR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001 reg.h  
1672
AR5K_PHY_CHAN_STATUS_RX_CLR_RAWAR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002 reg.h  
1673
AR5K_PHY_CHAN_STATUS_RX_CLR_MACAR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004 reg.h  
1674
AR5K_PHY_CHAN_STATUS_RX_CLR_PAPAR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008 reg.h  
1675
AR5K_PHY_HEAVY_CLIP_ENABLEAR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0 reg.h  
1676
AR5K_PHY_SCLOCKAR5K_PHY_SCLOCK 0x99f0 reg.h  
1677
AR5K_PHY_SCLOCK_32MHZAR5K_PHY_SCLOCK_32MHZ 0x0000000c reg.h  
1678
AR5K_PHY_SDELAYAR5K_PHY_SDELAY 0x99f4 reg.h  
1679
AR5K_PHY_SDELAY_32MHZAR5K_PHY_SDELAY_32MHZ 0x000000ff reg.h  
1680
AR5K_PHY_SPENDINGAR5K_PHY_SPENDING 0x99f8 reg.h  
1681
AR5K_PHY_PAPD_I_BASEAR5K_PHY_PAPD_I_BASE 0xa000 reg.h  
1682
AR5K_PHY_PCDAC_TXPOWER_BASEAR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 reg.h  
1683
AR5K_PHY_MODEAR5K_PHY_MODE 0x0a200 reg.h Register Address
1684
AR5K_PHY_MODE_MODAR5K_PHY_MODE_MOD 0x00000001 reg.h PHY Modulation bit
1685
AR5K_PHY_MODE_MOD_OFDMAR5K_PHY_MODE_MOD_OFDM 0 reg.h  
1686
AR5K_PHY_MODE_MOD_CCKAR5K_PHY_MODE_MOD_CCK 1 reg.h  
1687
AR5K_PHY_MODE_FREQAR5K_PHY_MODE_FREQ 0x00000002 reg.h Freq mode bit
1688
AR5K_PHY_MODE_FREQ_5GHZAR5K_PHY_MODE_FREQ_5GHZ 0 reg.h  
1689
AR5K_PHY_MODE_FREQ_2GHZAR5K_PHY_MODE_FREQ_2GHZ 2 reg.h  
1690
AR5K_PHY_MODE_MOD_DYNAR5K_PHY_MODE_MOD_DYN 0x00000004 reg.h Enable Dynamic OFDM/CCK mode [5112+]
1691
AR5K_PHY_MODE_RADAR5K_PHY_MODE_RAD 0x00000008 reg.h [5212+]
1692
AR5K_PHY_MODE_RAD_RF5111AR5K_PHY_MODE_RAD_RF5111 0 reg.h  
1693
AR5K_PHY_MODE_RAD_RF5112AR5K_PHY_MODE_RAD_RF5112 8 reg.h  
1694
AR5K_PHY_MODE_XRAR5K_PHY_MODE_XR 0x00000010 reg.h Enable XR mode [5112+]
1695
AR5K_PHY_MODE_HALF_RATEAR5K_PHY_MODE_HALF_RATE 0x00000020 reg.h Enable Half rate (test)
1696
AR5K_PHY_MODE_QUARTER_RATEAR5K_PHY_MODE_QUARTER_RATE 0x00000040 reg.h Enable Quarter rat (test)
1697
AR5K_PHY_CCKTXCTLAR5K_PHY_CCKTXCTL 0xa204 reg.h  
1698
AR5K_PHY_CCKTXCTL_WORLDAR5K_PHY_CCKTXCTL_WORLD 0x00000000 reg.h  
1699
AR5K_PHY_CCKTXCTL_JAPANAR5K_PHY_CCKTXCTL_JAPAN 0x00000010 reg.h  
1700
AR5K_PHY_CCKTXCTL_SCRAMBLER_DISAR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001 reg.h  
1701
AR5K_PHY_CCKTXCTK_DAC_SCALEAR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004 reg.h  
1702
AR5K_PHY_CCK_CROSSCORRAR5K_PHY_CCK_CROSSCORR 0xa208 reg.h  
1703
AR5K_PHY_CCK_CROSSCORR_WEAK_SIGAR5K_PHY_CCK_CROSSCORR_WEAK_SIG 0x0000000f reg.h  
1704
AR5K_PHY_CCK_CROSSCORR_WEAK_SIGAR5K_PHY_CCK_CROSSCORR_WEAK_SIG 0 reg.h  
1705
AR5K_PHY_FAST_ANT_DIVAR5K_PHY_FAST_ANT_DIV 0xa208 reg.h  
1706
AR5K_PHY_FAST_ANT_DIV_ENAR5K_PHY_FAST_ANT_DIV_EN 0x00002000 reg.h  
1707
AR5K_PHY_GAIN_2GHZAR5K_PHY_GAIN_2GHZ 0xa20c reg.h  
1708
AR5K_PHY_GAIN_2GHZ_MARGIN_TXRXAR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 reg.h  
1709
AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_ 18 reg.h  
1710
AR5K_PHY_GAIN_2GHZ_INI_5111AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c reg.h  
1711
AR5K_PHY_CCK_RX_CTL_4AR5K_PHY_CCK_RX_CTL_4 0xa21c reg.h  
1712
AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_ 0x01f80000 reg.h  
1713
AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_ 19 reg.h  
1714
AR5K_PHY_DAG_CCK_CTLAR5K_PHY_DAG_CCK_CTL 0xa228 reg.h  
1715
AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THAR5K_PHY_DAG_CCK_CTL_EN_RSSI_TH 0x00000200 reg.h  
1716
AR5K_PHY_DAG_CCK_CTL_RSSI_THRAR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00 reg.h  
1717
AR5K_PHY_DAG_CCK_CTL_RSSI_THR_SAR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10 reg.h  
1718
AR5K_PHY_FAST_ADCAR5K_PHY_FAST_ADC 0xa24c reg.h  
1719
AR5K_PHY_BLUETOOTHAR5K_PHY_BLUETOOTH 0xa254 reg.h  
1720
AR5K_PHY_TPC_RG1AR5K_PHY_TPC_RG1 0xa258 reg.h  
1721
AR5K_PHY_TPC_RG1_NUM_PD_GAINAR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000 reg.h  
1722
AR5K_PHY_TPC_RG1_NUM_PD_GAIN_SAR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14 reg.h  
1723
AR5K_PHY_TPC_RG1_PDGAIN_1AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000 reg.h  
1724
AR5K_PHY_TPC_RG1_PDGAIN_1_SAR5K_PHY_TPC_RG1_PDGAIN_1_S 16 reg.h  
1725
AR5K_PHY_TPC_RG1_PDGAIN_2AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000 reg.h  
1726
AR5K_PHY_TPC_RG1_PDGAIN_2_SAR5K_PHY_TPC_RG1_PDGAIN_2_S 18 reg.h  
1727
AR5K_PHY_TPC_RG1_PDGAIN_3AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000 reg.h  
1728
AR5K_PHY_TPC_RG1_PDGAIN_3_SAR5K_PHY_TPC_RG1_PDGAIN_3_S 20 reg.h  
1729
AR5K_PHY_TPC_RG5AR5K_PHY_TPC_RG5 0xa26C reg.h  
1730
AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAAR5K_PHY_TPC_RG5_PD_GAIN_OVERLA 0x0000000F reg.h  
1731
AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAAR5K_PHY_TPC_RG5_PD_GAIN_OVERLA 0 reg.h  
1732
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x000003F0 reg.h  
1733
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 4 reg.h  
1734
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x0000FC00 reg.h  
1735
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 10 reg.h  
1736
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x003F0000 reg.h  
1737
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 16 reg.h  
1738
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x0FC00000 reg.h  
1739
AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 22 reg.h  
1740
AR5K_PHY_PDADC_TXPOWER_BASEAR5K_PHY_PDADC_TXPOWER_BASE 0xa280 reg.h  
1741
AR5K_RF5111_OB_2GHZAR5K_RF5111_OB_2GHZ { 3, 119, 0 } rfbuffer.h  
1742
AR5K_RF5111_DB_2GHZAR5K_RF5111_DB_2GHZ { 3, 122, 0 } rfbuffer.h  
1743
AR5K_RF5111_OB_5GHZAR5K_RF5111_OB_5GHZ { 3, 104, 0 } rfbuffer.h  
1744
AR5K_RF5111_DB_5GHZAR5K_RF5111_DB_5GHZ { 3, 107, 0 } rfbuffer.h  
1745
AR5K_RF5111_PWD_XPDAR5K_RF5111_PWD_XPD { 1, 95, 0 } rfbuffer.h  
1746
AR5K_RF5111_XPD_GAINAR5K_RF5111_XPD_GAIN { 4, 96, 0 } rfbuffer.h  
1747
AR5K_RF5111_GAIN_IAR5K_RF5111_GAIN_I { 6, 29, 0 } rfbuffer.h  
1748
AR5K_RF5111_PLO_SELAR5K_RF5111_PLO_SEL { 1, 4, 0 } rfbuffer.h  
1749
AR5K_RF5111_RFGAIN_SELAR5K_RF5111_RFGAIN_SEL { 1, 36, 0 } rfbuffer.h  
1750
AR5K_RF5111_RFGAIN_STEPAR5K_RF5111_RFGAIN_STEP { 6, 37, 0 } rfbuffer.h  
1751
AR5K_RF5111_WAIT_SAR5K_RF5111_WAIT_S { 5, 19, 0 } rfbuffer.h  
1752
AR5K_RF5111_WAIT_IAR5K_RF5111_WAIT_I { 5, 24, 0 } rfbuffer.h  
1753
AR5K_RF5111_MAX_TIMEAR5K_RF5111_MAX_TIME { 2, 49, 0 } rfbuffer.h  
1754
AR5K_RF5112X_GAIN_IAR5K_RF5112X_GAIN_I { 6, 14, 0 } rfbuffer.h  
1755
AR5K_RF5112X_MIXVGA_OVRAR5K_RF5112X_MIXVGA_OVR { 1, 36, 0 } rfbuffer.h  
1756
AR5K_RF5112X_MIXGAIN_OVRAR5K_RF5112X_MIXGAIN_OVR { 2, 37, 0 } rfbuffer.h  
1757
AR5K_RF5112X_MIXGAIN_STEPAR5K_RF5112X_MIXGAIN_STEP { 4, 32, 0 } rfbuffer.h  
1758
AR5K_RF5112X_PD_DELAY_AAR5K_RF5112X_PD_DELAY_A { 4, 58, 0 } rfbuffer.h  
1759
AR5K_RF5112X_PD_DELAY_BAR5K_RF5112X_PD_DELAY_B { 4, 62, 0 } rfbuffer.h  
1760
AR5K_RF5112X_PD_DELAY_XRAR5K_RF5112X_PD_DELAY_XR { 4, 66, 0 } rfbuffer.h  
1761
AR5K_RF5112X_PD_PERIOD_AAR5K_RF5112X_PD_PERIOD_A { 4, 70, 0 } rfbuffer.h  
1762
AR5K_RF5112X_PD_PERIOD_BAR5K_RF5112X_PD_PERIOD_B { 4, 74, 0 } rfbuffer.h  
1763
AR5K_RF5112X_PD_PERIOD_XRAR5K_RF5112X_PD_PERIOD_XR { 4, 78, 0 } rfbuffer.h  
1764
AR5K_RF5112_OB_2GHZAR5K_RF5112_OB_2GHZ { 3, 269, 0 } rfbuffer.h  
1765
AR5K_RF5112_DB_2GHZAR5K_RF5112_DB_2GHZ { 3, 272, 0 } rfbuffer.h  
1766
AR5K_RF5112_OB_5GHZAR5K_RF5112_OB_5GHZ { 3, 261, 0 } rfbuffer.h  
1767
AR5K_RF5112_DB_5GHZAR5K_RF5112_DB_5GHZ { 3, 264, 0 } rfbuffer.h  
1768
AR5K_RF5112_FIXED_BIAS_AAR5K_RF5112_FIXED_BIAS_A { 1, 260, 0 } rfbuffer.h  
1769
AR5K_RF5112_FIXED_BIAS_BAR5K_RF5112_FIXED_BIAS_B { 1, 259, 0 } rfbuffer.h  
1770
AR5K_RF5112_XPD_SELAR5K_RF5112_XPD_SEL { 1, 284, 0 } rfbuffer.h  
1771
AR5K_RF5112_XPD_GAINAR5K_RF5112_XPD_GAIN { 2, 252, 0 } rfbuffer.h  
1772
AR5K_RF5112A_OB_2GHZAR5K_RF5112A_OB_2GHZ { 3, 287, 0 } rfbuffer.h  
1773
AR5K_RF5112A_DB_2GHZAR5K_RF5112A_DB_2GHZ { 3, 290, 0 } rfbuffer.h  
1774
AR5K_RF5112A_OB_5GHZAR5K_RF5112A_OB_5GHZ { 3, 279, 0 } rfbuffer.h  
1775
AR5K_RF5112A_DB_5GHZAR5K_RF5112A_DB_5GHZ { 3, 282, 0 } rfbuffer.h  
1776
AR5K_RF5112A_FIXED_BIAS_AAR5K_RF5112A_FIXED_BIAS_A { 1, 278, 0 } rfbuffer.h  
1777
AR5K_RF5112A_FIXED_BIAS_BAR5K_RF5112A_FIXED_BIAS_B { 1, 277, 0 } rfbuffer.h  
1778
AR5K_RF5112A_XPD_SELAR5K_RF5112A_XPD_SEL { 1, 302, 0 } rfbuffer.h  
1779
AR5K_RF5112A_PDGAINLOAR5K_RF5112A_PDGAINLO { 2, 270, 0 } rfbuffer.h  
1780
AR5K_RF5112A_PDGAINHIAR5K_RF5112A_PDGAINHI { 2, 257, 0 } rfbuffer.h  
1781
AR5K_RF5112A_HIGH_VC_CPAR5K_RF5112A_HIGH_VC_CP { 2, 90, 2 } rfbuffer.h  
1782
AR5K_RF5112A_MID_VC_CPAR5K_RF5112A_MID_VC_CP { 2, 92, 2 } rfbuffer.h  
1783
AR5K_RF5112A_LOW_VC_CPAR5K_RF5112A_LOW_VC_CP { 2, 94, 2 } rfbuffer.h  
1784
AR5K_RF5112A_PUSH_UPAR5K_RF5112A_PUSH_UP { 1, 254, 2 } rfbuffer.h  
1785
AR5K_RF5112A_PAD2GNDAR5K_RF5112A_PAD2GND { 1, 281, 1 } rfbuffer.h  
1786
AR5K_RF5112A_XB2_LVLAR5K_RF5112A_XB2_LVL { 2, 1, 3 } rfbuffer.h  
1787
AR5K_RF5112A_XB5_LVLAR5K_RF5112A_XB5_LVL { 2, 3, 3 } rfbuffer.h  
1788
AR5K_RF2413_OB_2GHZAR5K_RF2413_OB_2GHZ { 3, 168, 0 } rfbuffer.h  
1789
AR5K_RF2413_DB_2GHZAR5K_RF2413_DB_2GHZ { 3, 165, 0 } rfbuffer.h  
1790
AR5K_RF2316_OB_2GHZAR5K_RF2316_OB_2GHZ { 3, 178, 0 } rfbuffer.h  
1791
AR5K_RF2316_DB_2GHZAR5K_RF2316_DB_2GHZ { 3, 175, 0 } rfbuffer.h  
1792
AR5K_RF5413_OB_2GHZAR5K_RF5413_OB_2GHZ { 3, 241, 0 } rfbuffer.h  
1793
AR5K_RF5413_DB_2GHZAR5K_RF5413_DB_2GHZ { 3, 238, 0 } rfbuffer.h  
1794
AR5K_RF5413_OB_5GHZAR5K_RF5413_OB_5GHZ { 3, 247, 0 } rfbuffer.h  
1795
AR5K_RF5413_DB_5GHZAR5K_RF5413_DB_5GHZ { 3, 244, 0 } rfbuffer.h  
1796
AR5K_RF5413_PWD_ICLOBUF2GAR5K_RF5413_PWD_ICLOBUF2G { 3, 131, 3 } rfbuffer.h  
1797
AR5K_RF5413_DERBY_CHAN_SEL_MODEAR5K_RF5413_DERBY_CHAN_SEL_MODE { 1, 291, 2 } rfbuffer.h  
1798
AR5K_RF2425_OB_2GHZAR5K_RF2425_OB_2GHZ { 3, 193, 0 } rfbuffer.h  
1799
AR5K_RF2425_DB_2GHZAR5K_RF2425_DB_2GHZ { 3, 190, 0 } rfbuffer.h  
1800
AR5K_GAIN_CRN_FIX_BITS_5111AR5K_GAIN_CRN_FIX_BITS_5111 4 rfgain.h  
1801
AR5K_GAIN_CRN_FIX_BITS_5112AR5K_GAIN_CRN_FIX_BITS_5112 7 rfgain.h  
1802
AR5K_GAIN_CRN_MAX_FIX_BITSAR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 rfgain.h  
1803
AR5K_GAIN_DYN_ADJUST_HI_MARGINAR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 rfgain.h  
1804
AR5K_GAIN_DYN_ADJUST_LO_MARGINAR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 rfgain.h  
1805
AR5K_GAIN_CCK_PROBE_CORRAR5K_GAIN_CCK_PROBE_CORR 5 rfgain.h  
1806
AR5K_GAIN_CCK_OFDM_GAIN_DELTAAR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 rfgain.h  
1807
AR5K_GAIN_STEP_COUNTAR5K_GAIN_STEP_COUNT 10 rfgain.h  
1808
BAR_0BAR_0 0 e1000.h  
1809
BAR_1BAR_1 1 e1000.h  
1810
BAR_5BAR_5 5 e1000.h  
1811
E1000_RXBUFFER_128E1000_RXBUFFER_128 128 e1000.h Used for packet split
1812
E1000_RXBUFFER_256E1000_RXBUFFER_256 256 e1000.h Used for packet split
1813
E1000_RXBUFFER_512E1000_RXBUFFER_512 512 e1000.h  
1814
E1000_RXBUFFER_1024E1000_RXBUFFER_1024 1024 e1000.h  
1815
E1000_RXBUFFER_2048E1000_RXBUFFER_2048 2048 e1000.h  
1816
E1000_RXBUFFER_4096E1000_RXBUFFER_4096 4096 e1000.h  
1817
E1000_RXBUFFER_8192E1000_RXBUFFER_8192 8192 e1000.h  
1818
E1000_RXBUFFER_16384E1000_RXBUFFER_16384 16384 e1000.h  
1819
E1000_SMARTSPEED_DOWNSHIFTE1000_SMARTSPEED_DOWNSHIFT 3 e1000.h  
1820
E1000_SMARTSPEED_MAXE1000_SMARTSPEED_MAX 15 e1000.h  
1821
E1000_PBA_BYTES_SHIFTE1000_PBA_BYTES_SHIFT 0xA e1000.h  
1822
E1000_TX_HEAD_ADDR_SHIFTE1000_TX_HEAD_ADDR_SHIFT 7 e1000.h  
1823
E1000_PBA_TX_MASKE1000_PBA_TX_MASK 0xFFFF0000 e1000.h  
1824
E1000_FC_HIGH_DIFFE1000_FC_HIGH_DIFF 0x1638 e1000.h High: 5688 bytes below Rx FIFO size
1825
E1000_FC_LOW_DIFFE1000_FC_LOW_DIFF 0x1640 e1000.h Low: 5696 bytes below Rx FIFO size
1826
E1000_FC_PAUSE_TIMEE1000_FC_PAUSE_TIME 0x0680 e1000.h 858 usec
1827
MAXIMUM_ETHERNET_VLAN_SIZEMAXIMUM_ETHERNET_VLAN_SIZE 1522 e1000.h  
1828
E1000_TX_QUEUE_WAKEE1000_TX_QUEUE_WAKE 16 e1000.h  
1829
E1000_RX_BUFFER_WRITEE1000_RX_BUFFER_WRITE 16 e1000.h Must be power of 2
1830
AUTO_ALL_MODESAUTO_ALL_MODES 0 e1000.h  
1831
E1000_EEPROM_82544_APME1000_EEPROM_82544_APM 0x0004 e1000.h  
1832
E1000_EEPROM_ICH8_APMEE1000_EEPROM_ICH8_APME 0x0004 e1000.h  
1833
E1000_EEPROM_APMEE1000_EEPROM_APME 0x0400 e1000.h  
1834
E1000_MASTER_SLAVEE1000_MASTER_SLAVE e1000_ms_hw_default e1000.h  
1835
E1000_MNG2HOST_PORT_623E1000_MNG2HOST_PORT_623 (1 << 5) e1000.h  
1836
E1000_MNG2HOST_PORT_664E1000_MNG2HOST_PORT_664 (1 << 6) e1000.h  
1837
E1000_ERT_2048E1000_ERT_2048 0x100 e1000.h  
1838
IORESOURCE_IOIORESOURCE_IO 0x00000100 e1000.h  
1839
IORESOURCE_MEMIORESOURCE_MEM 0x00000200 e1000.h  
1840
IORESOURCE_PREFETCHIORESOURCE_PREFETCH 0x00001000 e1000.h  
1841
E1000_HOST_IF_MAX_SIZEE1000_HOST_IF_MAX_SIZE 2048 e1000_hw.h  
1842
E1000_SUCCESSE1000_SUCCESS 0 e1000_hw.h  
1843
E1000_ERR_EEPROME1000_ERR_EEPROM 1 e1000_hw.h  
1844
E1000_ERR_PHYE1000_ERR_PHY 2 e1000_hw.h  
1845
E1000_ERR_CONFIGE1000_ERR_CONFIG 3 e1000_hw.h  
1846
E1000_ERR_PARAME1000_ERR_PARAM 4 e1000_hw.h  
1847
E1000_ERR_MAC_TYPEE1000_ERR_MAC_TYPE 5 e1000_hw.h  
1848
E1000_ERR_PHY_TYPEE1000_ERR_PHY_TYPE 6 e1000_hw.h  
1849
E1000_ERR_RESETE1000_ERR_RESET 9 e1000_hw.h  
1850
E1000_ERR_MASTER_REQUESTS_PENDIE1000_ERR_MASTER_REQUESTS_PENDI 10 e1000_hw.h  
1851
E1000_ERR_HOST_INTERFACE_COMMANE1000_ERR_HOST_INTERFACE_COMMAN 11 e1000_hw.h  
1852
E1000_BLK_PHY_RESETE1000_BLK_PHY_RESET 12 e1000_hw.h  
1853
E1000_ERR_SWFW_SYNCE1000_ERR_SWFW_SYNC 13 e1000_hw.h  
1854
E1000_MNG_DHCP_TX_PAYLOAD_CMDE1000_MNG_DHCP_TX_PAYLOAD_CMD 64 e1000_hw.h  
1855
E1000_HI_MAX_MNG_DATA_LENGTHE1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 e1000_hw.h Host Interface data length
1856
E1000_MNG_DHCP_COMMAND_TIMEOUTE1000_MNG_DHCP_COMMAND_TIMEOUT 10 e1000_hw.h Time in ms to process MNG command
1857
E1000_MNG_DHCP_COOKIE_OFFSETE1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 e1000_hw.h Cookie offset
1858
E1000_MNG_DHCP_COOKIE_LENGTHE1000_MNG_DHCP_COOKIE_LENGTH 0x10 e1000_hw.h Cookie length
1859
E1000_MNG_IAMT_MODEE1000_MNG_IAMT_MODE 0x3 e1000_hw.h  
1860
E1000_MNG_ICH_IAMT_MODEE1000_MNG_ICH_IAMT_MODE 0x2 e1000_hw.h  
1861
E1000_IAMT_SIGNATUREE1000_IAMT_SIGNATURE 0x544D4149 e1000_hw.h Intel(R) Active Management Technology signature
1862
E1000_MNG_DHCP_COOKIE_STATUS_PAE1000_MNG_DHCP_COOKIE_STATUS_PA 0x1 e1000_hw.h DHCP parsing enabled
1863
E1000_MNG_DHCP_COOKIE_STATUS_VLE1000_MNG_DHCP_COOKIE_STATUS_VL 0x2 e1000_hw.h DHCP parsing enabled
1864
E1000_VFTA_ENTRY_SHIFTE1000_VFTA_ENTRY_SHIFT 0x5 e1000_hw.h  
1865
E1000_VFTA_ENTRY_MASKE1000_VFTA_ENTRY_MASK 0x7F e1000_hw.h  
1866
E1000_VFTA_ENTRY_BIT_SHIFT_MASKE1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F e1000_hw.h  
1867
E1000_DEV_ID_82542E1000_DEV_ID_82542 0x1000 e1000_hw.h  
1868
E1000_DEV_ID_82543GC_FIBERE1000_DEV_ID_82543GC_FIBER 0x1001 e1000_hw.h  
1869
E1000_DEV_ID_82543GC_COPPERE1000_DEV_ID_82543GC_COPPER 0x1004 e1000_hw.h  
1870
E1000_DEV_ID_82544EI_COPPERE1000_DEV_ID_82544EI_COPPER 0x1008 e1000_hw.h  
1871
E1000_DEV_ID_82544EI_FIBERE1000_DEV_ID_82544EI_FIBER 0x1009 e1000_hw.h  
1872
E1000_DEV_ID_82544GC_COPPERE1000_DEV_ID_82544GC_COPPER 0x100C e1000_hw.h  
1873
E1000_DEV_ID_82544GC_LOME1000_DEV_ID_82544GC_LOM 0x100D e1000_hw.h  
1874
E1000_DEV_ID_82540EME1000_DEV_ID_82540EM 0x100E e1000_hw.h  
1875
E1000_DEV_ID_82540EM_LOME1000_DEV_ID_82540EM_LOM 0x1015 e1000_hw.h  
1876
E1000_DEV_ID_82540EP_LOME1000_DEV_ID_82540EP_LOM 0x1016 e1000_hw.h  
1877
E1000_DEV_ID_82540EPE1000_DEV_ID_82540EP 0x1017 e1000_hw.h  
1878
E1000_DEV_ID_82540EP_LPE1000_DEV_ID_82540EP_LP 0x101E e1000_hw.h  
1879
E1000_DEV_ID_82545EM_COPPERE1000_DEV_ID_82545EM_COPPER 0x100F e1000_hw.h  
1880
E1000_DEV_ID_82545EM_FIBERE1000_DEV_ID_82545EM_FIBER 0x1011 e1000_hw.h  
1881
E1000_DEV_ID_82545GM_COPPERE1000_DEV_ID_82545GM_COPPER 0x1026 e1000_hw.h  
1882
E1000_DEV_ID_82545GM_FIBERE1000_DEV_ID_82545GM_FIBER 0x1027 e1000_hw.h  
1883
E1000_DEV_ID_82545GM_SERDESE1000_DEV_ID_82545GM_SERDES 0x1028 e1000_hw.h  
1884
E1000_DEV_ID_82546EB_COPPERE1000_DEV_ID_82546EB_COPPER 0x1010 e1000_hw.h  
1885
E1000_DEV_ID_82546EB_FIBERE1000_DEV_ID_82546EB_FIBER 0x1012 e1000_hw.h  
1886
E1000_DEV_ID_82546EB_QUAD_COPPEE1000_DEV_ID_82546EB_QUAD_COPPE 0x101D e1000_hw.h  
1887
E1000_DEV_ID_82541EIE1000_DEV_ID_82541EI 0x1013 e1000_hw.h  
1888
E1000_DEV_ID_82541EI_MOBILEE1000_DEV_ID_82541EI_MOBILE 0x1018 e1000_hw.h  
1889
E1000_DEV_ID_82541ER_LOME1000_DEV_ID_82541ER_LOM 0x1014 e1000_hw.h  
1890
E1000_DEV_ID_82541ERE1000_DEV_ID_82541ER 0x1078 e1000_hw.h  
1891
E1000_DEV_ID_82547GIE1000_DEV_ID_82547GI 0x1075 e1000_hw.h  
1892
E1000_DEV_ID_82541GIE1000_DEV_ID_82541GI 0x1076 e1000_hw.h  
1893
E1000_DEV_ID_82541GI_MOBILEE1000_DEV_ID_82541GI_MOBILE 0x1077 e1000_hw.h  
1894
E1000_DEV_ID_82541GI_LFE1000_DEV_ID_82541GI_LF 0x107C e1000_hw.h  
1895
E1000_DEV_ID_82546GB_COPPERE1000_DEV_ID_82546GB_COPPER 0x1079 e1000_hw.h  
1896
E1000_DEV_ID_82546GB_FIBERE1000_DEV_ID_82546GB_FIBER 0x107A e1000_hw.h  
1897
E1000_DEV_ID_82546GB_SERDESE1000_DEV_ID_82546GB_SERDES 0x107B e1000_hw.h  
1898
E1000_DEV_ID_82546GB_PCIEE1000_DEV_ID_82546GB_PCIE 0x108A e1000_hw.h  
1899
E1000_DEV_ID_82546GB_QUAD_COPPEE1000_DEV_ID_82546GB_QUAD_COPPE 0x1099 e1000_hw.h  
1900
E1000_DEV_ID_82547EIE1000_DEV_ID_82547EI 0x1019 e1000_hw.h  
1901
E1000_DEV_ID_82547EI_MOBILEE1000_DEV_ID_82547EI_MOBILE 0x101A e1000_hw.h  
1902
E1000_DEV_ID_82571EB_COPPERE1000_DEV_ID_82571EB_COPPER 0x105E e1000_hw.h  
1903
E1000_DEV_ID_82571EB_FIBERE1000_DEV_ID_82571EB_FIBER 0x105F e1000_hw.h  
1904
E1000_DEV_ID_82571EB_SERDESE1000_DEV_ID_82571EB_SERDES 0x1060 e1000_hw.h  
1905
E1000_DEV_ID_82571EB_QUAD_COPPEE1000_DEV_ID_82571EB_QUAD_COPPE 0x10A4 e1000_hw.h  
1906
E1000_DEV_ID_82571EB_QUAD_FIBERE1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 e1000_hw.h  
1907
E1000_DEV_ID_82571EB_QUAD_COPPEE1000_DEV_ID_82571EB_QUAD_COPPE 0x10BC e1000_hw.h  
1908
E1000_DEV_ID_82571EB_SERDES_DUAE1000_DEV_ID_82571EB_SERDES_DUA 0x10D9 e1000_hw.h  
1909
E1000_DEV_ID_82571EB_SERDES_QUAE1000_DEV_ID_82571EB_SERDES_QUA 0x10DA e1000_hw.h  
1910
E1000_DEV_ID_82572EI_COPPERE1000_DEV_ID_82572EI_COPPER 0x107D e1000_hw.h  
1911
E1000_DEV_ID_82572EI_FIBERE1000_DEV_ID_82572EI_FIBER 0x107E e1000_hw.h  
1912
E1000_DEV_ID_82572EI_SERDESE1000_DEV_ID_82572EI_SERDES 0x107F e1000_hw.h  
1913
E1000_DEV_ID_82572EIE1000_DEV_ID_82572EI 0x10B9 e1000_hw.h  
1914
E1000_DEV_ID_82573EE1000_DEV_ID_82573E 0x108B e1000_hw.h  
1915
E1000_DEV_ID_82573E_IAMTE1000_DEV_ID_82573E_IAMT 0x108C e1000_hw.h  
1916
E1000_DEV_ID_82573LE1000_DEV_ID_82573L 0x109A e1000_hw.h  
1917
E1000_DEV_ID_82546GB_QUAD_COPPEE1000_DEV_ID_82546GB_QUAD_COPPE 0x10B5 e1000_hw.h  
1918
E1000_DEV_ID_80003ES2LAN_COPPERE1000_DEV_ID_80003ES2LAN_COPPER 0x1096 e1000_hw.h  
1919
E1000_DEV_ID_80003ES2LAN_SERDESE1000_DEV_ID_80003ES2LAN_SERDES 0x1098 e1000_hw.h  
1920
E1000_DEV_ID_80003ES2LAN_COPPERE1000_DEV_ID_80003ES2LAN_COPPER 0x10BA e1000_hw.h  
1921
E1000_DEV_ID_80003ES2LAN_SERDESE1000_DEV_ID_80003ES2LAN_SERDES 0x10BB e1000_hw.h  
1922
E1000_DEV_ID_ICH8_IGP_M_AMTE1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 e1000_hw.h  
1923
E1000_DEV_ID_ICH8_IGP_AMTE1000_DEV_ID_ICH8_IGP_AMT 0x104A e1000_hw.h  
1924
E1000_DEV_ID_ICH8_IGP_CE1000_DEV_ID_ICH8_IGP_C 0x104B e1000_hw.h  
1925
E1000_DEV_ID_ICH8_IFEE1000_DEV_ID_ICH8_IFE 0x104C e1000_hw.h  
1926
E1000_DEV_ID_ICH8_IFE_GTE1000_DEV_ID_ICH8_IFE_GT 0x10C4 e1000_hw.h  
1927
E1000_DEV_ID_ICH8_IFE_GE1000_DEV_ID_ICH8_IFE_G 0x10C5 e1000_hw.h  
1928
E1000_DEV_ID_ICH8_IGP_ME1000_DEV_ID_ICH8_IGP_M 0x104D e1000_hw.h  
1929
E1000_DEV_ID_82576E1000_DEV_ID_82576 0x10C9 e1000_hw.h  
1930
NODE_ADDRESS_SIZENODE_ADDRESS_SIZE 6 e1000_hw.h  
1931
ETH_LENGTH_OF_ADDRESSETH_LENGTH_OF_ADDRESS 6 e1000_hw.h  
1932
MAC_DECODE_SIZEMAC_DECODE_SIZE (128 * 1024) e1000_hw.h  
1933
E1000_82542_2_0_REV_IDE1000_82542_2_0_REV_ID 2 e1000_hw.h  
1934
E1000_82542_2_1_REV_IDE1000_82542_2_1_REV_ID 3 e1000_hw.h  
1935
E1000_REVISION_0E1000_REVISION_0 0 e1000_hw.h  
1936
E1000_REVISION_1E1000_REVISION_1 1 e1000_hw.h  
1937
E1000_REVISION_2E1000_REVISION_2 2 e1000_hw.h  
1938
E1000_REVISION_3E1000_REVISION_3 3 e1000_hw.h  
1939
SPEED_10SPEED_10 10 e1000_hw.h  
1940
SPEED_100SPEED_100 100 e1000_hw.h  
1941
SPEED_1000SPEED_1000 1000 e1000_hw.h  
1942
HALF_DUPLEXHALF_DUPLEX 1 e1000_hw.h  
1943
FULL_DUPLEXFULL_DUPLEX 2 e1000_hw.h  
1944
ENET_HEADER_SIZEENET_HEADER_SIZE 14 e1000_hw.h  
1945
MAXIMUM_ETHERNET_FRAME_SIZEMAXIMUM_ETHERNET_FRAME_SIZE 1518 e1000_hw.h With FCS
1946
MINIMUM_ETHERNET_FRAME_SIZEMINIMUM_ETHERNET_FRAME_SIZE 64 e1000_hw.h With FCS
1947
ETHERNET_FCS_SIZEETHERNET_FCS_SIZE 4 e1000_hw.h  
1948
MAXIMUM_ETHERNET_PACKET_SIZEMAXIMUM_ETHERNET_PACKET_SIZE (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) e1000_hw.h  
1949
MINIMUM_ETHERNET_PACKET_SIZEMINIMUM_ETHERNET_PACKET_SIZE (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) e1000_hw.h  
1950
CRC_LENGTHCRC_LENGTH ETHERNET_FCS_SIZE e1000_hw.h  
1951
MAX_JUMBO_FRAME_SIZEMAX_JUMBO_FRAME_SIZE 0x3F00 e1000_hw.h  
1952
VLAN_TAG_SIZEVLAN_TAG_SIZE 4 e1000_hw.h 802.3ac tag (not DMAed)
1953
ETHERNET_IEEE_VLAN_TYPEETHERNET_IEEE_VLAN_TYPE 0x8100 e1000_hw.h 802.3ac packet
1954
ETHERNET_IP_TYPEETHERNET_IP_TYPE 0x0800 e1000_hw.h IP packets
1955
ETHERNET_ARP_TYPEETHERNET_ARP_TYPE 0x0806 e1000_hw.h Address Resolution Protocol (ARP)
1956
IP_PROTOCOL_TCPIP_PROTOCOL_TCP 6 e1000_hw.h  
1957
IP_PROTOCOL_UDPIP_PROTOCOL_UDP 0x11 e1000_hw.h  
1958
POLL_IMS_ENABLE_MASKPOLL_IMS_ENABLE_MASK ( \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ) e1000_hw.h  
1959
IMS_ENABLE_MASKIMS_ENABLE_MASK ( \ E1000_IMS_RXT0 | \ E1000_IMS_TXDW | \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ | \ E1000_IMS_LSC | \ E10 e1000_hw.h  
1960
IMS_ICH8LAN_ENABLE_MASKIMS_ICH8LAN_ENABLE_MASK (\ E1000_IMS_DSW | \ E1000_IMS_PHYINT | \ E1000_IMS_EPRST) e1000_hw.h  
1961
E1000_RAR_ENTRIESE1000_RAR_ENTRIES 15 e1000_hw.h  
1962
E1000_RAR_ENTRIES_ICH8LANE1000_RAR_ENTRIES_ICH8LAN 6 e1000_hw.h  
1963
MIN_NUMBER_OF_DESCRIPTORSMIN_NUMBER_OF_DESCRIPTORS 8 e1000_hw.h  
1964
MAX_NUMBER_OF_DESCRIPTORSMAX_NUMBER_OF_DESCRIPTORS 0xFFF8 e1000_hw.h  
1965
MAX_PS_BUFFERSMAX_PS_BUFFERS 4 e1000_hw.h  
1966
E1000_RXD_STAT_DDE1000_RXD_STAT_DD 0x01 e1000_hw.h Descriptor Done
1967
E1000_RXD_STAT_EOPE1000_RXD_STAT_EOP 0x02 e1000_hw.h End of Packet
1968
E1000_RXD_STAT_IXSME1000_RXD_STAT_IXSM 0x04 e1000_hw.h Ignore checksum
1969
E1000_RXD_STAT_VPE1000_RXD_STAT_VP 0x08 e1000_hw.h IEEE VLAN Packet
1970
E1000_RXD_STAT_UDPCSE1000_RXD_STAT_UDPCS 0x10 e1000_hw.h UDP xsum caculated
1971
E1000_RXD_STAT_TCPCSE1000_RXD_STAT_TCPCS 0x20 e1000_hw.h TCP xsum calculated
1972
E1000_RXD_STAT_IPCSE1000_RXD_STAT_IPCS 0x40 e1000_hw.h IP xsum calculated
1973
E1000_RXD_STAT_PIFE1000_RXD_STAT_PIF 0x80 e1000_hw.h passed in-exact filter
1974
E1000_RXD_STAT_IPIDVE1000_RXD_STAT_IPIDV 0x200 e1000_hw.h IP identification valid
1975
E1000_RXD_STAT_UDPVE1000_RXD_STAT_UDPV 0x400 e1000_hw.h Valid UDP checksum
1976
E1000_RXD_STAT_ACKE1000_RXD_STAT_ACK 0x8000 e1000_hw.h ACK Packet indication
1977
E1000_RXD_ERR_CEE1000_RXD_ERR_CE 0x01 e1000_hw.h CRC Error
1978
E1000_RXD_ERR_SEE1000_RXD_ERR_SE 0x02 e1000_hw.h Symbol Error
1979
E1000_RXD_ERR_SEQE1000_RXD_ERR_SEQ 0x04 e1000_hw.h Sequence Error
1980
E1000_RXD_ERR_CXEE1000_RXD_ERR_CXE 0x10 e1000_hw.h Carrier Extension Error
1981
E1000_RXD_ERR_TCPEE1000_RXD_ERR_TCPE 0x20 e1000_hw.h TCP/UDP Checksum Error
1982
E1000_RXD_ERR_IPEE1000_RXD_ERR_IPE 0x40 e1000_hw.h IP Checksum Error
1983
E1000_RXD_ERR_RXEE1000_RXD_ERR_RXE 0x80 e1000_hw.h Rx Data Error
1984
E1000_RXD_SPC_VLAN_MASKE1000_RXD_SPC_VLAN_MASK 0x0FFF e1000_hw.h VLAN ID is in lower 12 bits
1985
E1000_RXD_SPC_PRI_MASKE1000_RXD_SPC_PRI_MASK 0xE000 e1000_hw.h Priority is in upper 3 bits
1986
E1000_RXD_SPC_PRI_SHIFTE1000_RXD_SPC_PRI_SHIFT 13 e1000_hw.h  
1987
E1000_RXD_SPC_CFI_MASKE1000_RXD_SPC_CFI_MASK 0x1000 e1000_hw.h CFI is bit 12
1988
E1000_RXD_SPC_CFI_SHIFTE1000_RXD_SPC_CFI_SHIFT 12 e1000_hw.h  
1989
E1000_RXDEXT_STATERR_CEE1000_RXDEXT_STATERR_CE 0x01000000 e1000_hw.h  
1990
E1000_RXDEXT_STATERR_SEE1000_RXDEXT_STATERR_SE 0x02000000 e1000_hw.h  
1991
E1000_RXDEXT_STATERR_SEQE1000_RXDEXT_STATERR_SEQ 0x04000000 e1000_hw.h  
1992
E1000_RXDEXT_STATERR_CXEE1000_RXDEXT_STATERR_CXE 0x10000000 e1000_hw.h  
1993
E1000_RXDEXT_STATERR_TCPEE1000_RXDEXT_STATERR_TCPE 0x20000000 e1000_hw.h  
1994
E1000_RXDEXT_STATERR_IPEE1000_RXDEXT_STATERR_IPE 0x40000000 e1000_hw.h  
1995
E1000_RXDEXT_STATERR_RXEE1000_RXDEXT_STATERR_RXE 0x80000000 e1000_hw.h  
1996
E1000_RXDPS_HDRSTAT_HDRSPE1000_RXDPS_HDRSTAT_HDRSP 0x00008000 e1000_hw.h  
1997
E1000_RXDPS_HDRSTAT_HDRLEN_MASKE1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF e1000_hw.h  
1998
E1000_RXD_ERR_FRAME_ERR_MASKE1000_RXD_ERR_FRAME_ERR_MASK ( \ E1000_RXD_ERR_CE | \ E1000_RXD_ERR_SE | \ E1000_RXD_ERR_SEQ | \ E1000_RXD_ER e1000_hw.h  
1999
E1000_RXDEXT_ERR_FRAME_ERR_MASKE1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ E1000_RXDEXT_STATERR_CE | \ E1000_RXDEXT_STATERR_SE | \ E1000_RXDEXT_STATERR_SEQ | \ E10 e1000_hw.h  
2000
E1000_TXD_DTYP_DE1000_TXD_DTYP_D 0x00100000 e1000_hw.h Data Descriptor
2001
E1000_TXD_DTYP_CE1000_TXD_DTYP_C 0x00000000 e1000_hw.h Context Descriptor
2002
E1000_TXD_POPTS_IXSME1000_TXD_POPTS_IXSM 0x01 e1000_hw.h Insert IP checksum
2003
E1000_TXD_POPTS_TXSME1000_TXD_POPTS_TXSM 0x02 e1000_hw.h Insert TCP/UDP checksum
2004
E1000_TXD_CMD_EOPE1000_TXD_CMD_EOP 0x01000000 e1000_hw.h End of Packet
2005
E1000_TXD_CMD_IFCSE1000_TXD_CMD_IFCS 0x02000000 e1000_hw.h Insert FCS (Ethernet CRC)
2006
E1000_TXD_CMD_ICE1000_TXD_CMD_IC 0x04000000 e1000_hw.h Insert Checksum
2007
E1000_TXD_CMD_RSE1000_TXD_CMD_RS 0x08000000 e1000_hw.h Report Status
2008
E1000_TXD_CMD_RPSE1000_TXD_CMD_RPS 0x10000000 e1000_hw.h Report Packet Sent
2009
E1000_TXD_CMD_DEXTE1000_TXD_CMD_DEXT 0x20000000 e1000_hw.h Descriptor extension (0 = legacy)
2010
E1000_TXD_CMD_VLEE1000_TXD_CMD_VLE 0x40000000 e1000_hw.h Add VLAN tag
2011
E1000_TXD_CMD_IDEE1000_TXD_CMD_IDE 0x80000000 e1000_hw.h Enable Tidv register
2012
E1000_TXD_STAT_DDE1000_TXD_STAT_DD 0x00000001 e1000_hw.h Descriptor Done
2013
E1000_TXD_STAT_ECE1000_TXD_STAT_EC 0x00000002 e1000_hw.h Excess Collisions
2014
E1000_TXD_STAT_LCE1000_TXD_STAT_LC 0x00000004 e1000_hw.h Late Collisions
2015
E1000_TXD_STAT_TUE1000_TXD_STAT_TU 0x00000008 e1000_hw.h Transmit underrun
2016
E1000_TXD_CMD_TCPE1000_TXD_CMD_TCP 0x01000000 e1000_hw.h TCP packet
2017
E1000_TXD_CMD_IPE1000_TXD_CMD_IP 0x02000000 e1000_hw.h IP packet
2018
E1000_TXD_CMD_TSEE1000_TXD_CMD_TSE 0x04000000 e1000_hw.h TCP Seg enable
2019
E1000_TXD_STAT_TCE1000_TXD_STAT_TC 0x00000004 e1000_hw.h Tx Underrun
2020
E1000_NUM_UNICASTE1000_NUM_UNICAST 16 e1000_hw.h Unicast filter entries
2021
E1000_MC_TBL_SIZEE1000_MC_TBL_SIZE 128 e1000_hw.h Multicast Filter Table (4096 bits)
2022
E1000_VLAN_FILTER_TBL_SIZEE1000_VLAN_FILTER_TBL_SIZE 128 e1000_hw.h VLAN Filter Table (4096 bits)
2023
E1000_NUM_UNICAST_ICH8LANE1000_NUM_UNICAST_ICH8LAN 7 e1000_hw.h  
2024
E1000_MC_TBL_SIZE_ICH8LANE1000_MC_TBL_SIZE_ICH8LAN 32 e1000_hw.h  
2025
E1000_NUM_MTA_REGISTERSE1000_NUM_MTA_REGISTERS 128 e1000_hw.h  
2026
E1000_NUM_MTA_REGISTERS_ICH8LANE1000_NUM_MTA_REGISTERS_ICH8LAN 32 e1000_hw.h  
2027
E1000_WAKEUP_IP_ADDRESS_COUNT_ME1000_WAKEUP_IP_ADDRESS_COUNT_M 4 e1000_hw.h  
2028
E1000_IP4AT_SIZEE1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX e1000_hw.h  
2029
E1000_IP4AT_SIZE_ICH8LANE1000_IP4AT_SIZE_ICH8LAN 3 e1000_hw.h  
2030
E1000_IP6AT_SIZEE1000_IP6AT_SIZE 1 e1000_hw.h  
2031
E1000_FLEXIBLE_FILTER_COUNT_MAXE1000_FLEXIBLE_FILTER_COUNT_MAX 4 e1000_hw.h  
2032
E1000_FLEXIBLE_FILTER_SIZE_MAXE1000_FLEXIBLE_FILTER_SIZE_MAX 128 e1000_hw.h  
2033
E1000_FFLT_SIZEE1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX e1000_hw.h  
2034
E1000_FFMT_SIZEE1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX e1000_hw.h  
2035
E1000_FFVT_SIZEE1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX e1000_hw.h  
2036
E1000_DISABLE_SERDES_LOOPBACKE1000_DISABLE_SERDES_LOOPBACK 0x0400 e1000_hw.h  
2037
E1000_CTRLE1000_CTRL 0x00000 e1000_hw.h Device Control - RW
2038
E1000_CTRL_DUPE1000_CTRL_DUP 0x00004 e1000_hw.h Device Control Duplicate (Shadow) - RW
2039
E1000_STATUSE1000_STATUS 0x00008 e1000_hw.h Device Status - RO
2040
E1000_EECDE1000_EECD 0x00010 e1000_hw.h EEPROM/Flash Control - RW
2041
E1000_EERDE1000_EERD 0x00014 e1000_hw.h EEPROM Read - RW
2042
E1000_CTRL_EXTE1000_CTRL_EXT 0x00018 e1000_hw.h Extended Device Control - RW
2043
E1000_FLAE1000_FLA 0x0001C e1000_hw.h Flash Access - RW
2044
E1000_MDICE1000_MDIC 0x00020 e1000_hw.h MDI Control - RW
2045
E1000_SCTLE1000_SCTL 0x00024 e1000_hw.h SerDes Control - RW
2046
E1000_FEXTNVME1000_FEXTNVM 0x00028 e1000_hw.h Future Extended NVM register
2047
E1000_FCALE1000_FCAL 0x00028 e1000_hw.h Flow Control Address Low - RW
2048
E1000_FCAHE1000_FCAH 0x0002C e1000_hw.h Flow Control Address High -RW
2049
E1000_FCTE1000_FCT 0x00030 e1000_hw.h Flow Control Type - RW
2050
E1000_VETE1000_VET 0x00038 e1000_hw.h VLAN Ether Type - RW
2051
E1000_ICRE1000_ICR 0x000C0 e1000_hw.h Interrupt Cause Read - R/clr
2052
E1000_ITRE1000_ITR 0x000C4 e1000_hw.h Interrupt Throttling Rate - RW
2053
E1000_ICSE1000_ICS 0x000C8 e1000_hw.h Interrupt Cause Set - WO
2054
E1000_IMSE1000_IMS 0x000D0 e1000_hw.h Interrupt Mask Set - RW
2055
E1000_IMCE1000_IMC 0x000D8 e1000_hw.h Interrupt Mask Clear - WO
2056
E1000_IAME1000_IAM 0x000E0 e1000_hw.h Interrupt Acknowledge Auto Mask
2057
E1000_RCTLE1000_RCTL 0x00100 e1000_hw.h RX Control - RW
2058
E1000_RDTR1E1000_RDTR1 0x02820 e1000_hw.h RX Delay Timer (1) - RW
2059
E1000_RDBAL1E1000_RDBAL1 0x02900 e1000_hw.h RX Descriptor Base Address Low (1) - RW
2060
E1000_RDBAH1E1000_RDBAH1 0x02904 e1000_hw.h RX Descriptor Base Address High (1) - RW
2061
E1000_RDLEN1E1000_RDLEN1 0x02908 e1000_hw.h RX Descriptor Length (1) - RW
2062
E1000_RDH1E1000_RDH1 0x02910 e1000_hw.h RX Descriptor Head (1) - RW
2063
E1000_RDT1E1000_RDT1 0x02918 e1000_hw.h RX Descriptor Tail (1) - RW
2064
E1000_FCTTVE1000_FCTTV 0x00170 e1000_hw.h Flow Control Transmit Timer Value - RW
2065
E1000_TXCWE1000_TXCW 0x00178 e1000_hw.h TX Configuration Word - RW
2066
E1000_RXCWE1000_RXCW 0x00180 e1000_hw.h RX Configuration Word - RO
2067
E1000_TCTLE1000_TCTL 0x00400 e1000_hw.h TX Control - RW
2068
E1000_TCTL_EXTE1000_TCTL_EXT 0x00404 e1000_hw.h Extended TX Control - RW
2069
E1000_TIPGE1000_TIPG 0x00410 e1000_hw.h TX Inter-packet gap -RW
2070
E1000_TBTE1000_TBT 0x00448 e1000_hw.h TX Burst Timer - RW
2071
E1000_AITE1000_AIT 0x00458 e1000_hw.h Adaptive Interframe Spacing Throttle - RW
2072
E1000_LEDCTLE1000_LEDCTL 0x00E00 e1000_hw.h LED Control - RW
2073
E1000_EXTCNF_CTRLE1000_EXTCNF_CTRL 0x00F00 e1000_hw.h Extended Configuration Control
2074
E1000_EXTCNF_SIZEE1000_EXTCNF_SIZE 0x00F08 e1000_hw.h Extended Configuration Size
2075
E1000_PHY_CTRLE1000_PHY_CTRL 0x00F10 e1000_hw.h PHY Control Register in CSR
2076
FEXTNVM_SW_CONFIGFEXTNVM_SW_CONFIG 0x0001 e1000_hw.h  
2077
E1000_PBAE1000_PBA 0x01000 e1000_hw.h Packet Buffer Allocation - RW
2078
E1000_PBSE1000_PBS 0x01008 e1000_hw.h Packet Buffer Size
2079
E1000_EEMNGCTLE1000_EEMNGCTL 0x01010 e1000_hw.h MNG EEprom Control
2080
E1000_FLASH_UPDATESE1000_FLASH_UPDATES 1000 e1000_hw.h  
2081
E1000_EEARBCE1000_EEARBC 0x01024 e1000_hw.h EEPROM Auto Read Bus Control
2082
E1000_FLASHTE1000_FLASHT 0x01028 e1000_hw.h FLASH Timer Register
2083
E1000_EEWRE1000_EEWR 0x0102C e1000_hw.h EEPROM Write Register - RW
2084
E1000_FLSWCTLE1000_FLSWCTL 0x01030 e1000_hw.h FLASH control register
2085
E1000_FLSWDATAE1000_FLSWDATA 0x01034 e1000_hw.h FLASH data register
2086
E1000_FLSWCNTE1000_FLSWCNT 0x01038 e1000_hw.h FLASH Access Counter
2087
E1000_FLOPE1000_FLOP 0x0103C e1000_hw.h FLASH Opcode Register
2088
E1000_ERTE1000_ERT 0x02008 e1000_hw.h Early Rx Threshold - RW
2089
E1000_FCRTLE1000_FCRTL 0x02160 e1000_hw.h Flow Control Receive Threshold Low - RW
2090
E1000_FCRTHE1000_FCRTH 0x02168 e1000_hw.h Flow Control Receive Threshold High - RW
2091
E1000_PSRCTLE1000_PSRCTL 0x02170 e1000_hw.h Packet Split Receive Control - RW
2092
E1000_RDBALE1000_RDBAL 0x02800 e1000_hw.h RX Descriptor Base Address Low - RW
2093
E1000_RDBAHE1000_RDBAH 0x02804 e1000_hw.h RX Descriptor Base Address High - RW
2094
E1000_RDLENE1000_RDLEN 0x02808 e1000_hw.h RX Descriptor Length - RW
2095
E1000_RDHE1000_RDH 0x02810 e1000_hw.h RX Descriptor Head - RW
2096
E1000_RDTE1000_RDT 0x02818 e1000_hw.h RX Descriptor Tail - RW
2097
E1000_RDTRE1000_RDTR 0x02820 e1000_hw.h RX Delay Timer - RW
2098
E1000_RDBAL0E1000_RDBAL0 E1000_RDBAL e1000_hw.h RX Desc Base Address Low (0) - RW
2099
E1000_RDBAH0E1000_RDBAH0 E1000_RDBAH e1000_hw.h RX Desc Base Address High (0) - RW
2100
E1000_RDLEN0E1000_RDLEN0 E1000_RDLEN e1000_hw.h RX Desc Length (0) - RW
2101
E1000_RDH0E1000_RDH0 E1000_RDH e1000_hw.h RX Desc Head (0) - RW
2102
E1000_RDT0E1000_RDT0 E1000_RDT e1000_hw.h RX Desc Tail (0) - RW
2103
E1000_RDTR0E1000_RDTR0 E1000_RDTR e1000_hw.h RX Delay Timer (0) - RW
2104
E1000_RXDCTLE1000_RXDCTL 0x02828 e1000_hw.h RX Descriptor Control queue 0 - RW
2105
E1000_RXDCTL1E1000_RXDCTL1 0x02928 e1000_hw.h RX Descriptor Control queue 1 - RW
2106
E1000_RADVE1000_RADV 0x0282C e1000_hw.h RX Interrupt Absolute Delay Timer - RW
2107
E1000_RSRPDE1000_RSRPD 0x02C00 e1000_hw.h RX Small Packet Detect - RW
2108
E1000_RAIDE1000_RAID 0x02C08 e1000_hw.h Receive Ack Interrupt Delay - RW
2109
E1000_TXDMACE1000_TXDMAC 0x03000 e1000_hw.h TX DMA Control - RW
2110
E1000_KABGTXDE1000_KABGTXD 0x03004 e1000_hw.h AFE Band Gap Transmit Ref Data
2111
E1000_TDFHE1000_TDFH 0x03410 e1000_hw.h TX Data FIFO Head - RW
2112
E1000_TDFTE1000_TDFT 0x03418 e1000_hw.h TX Data FIFO Tail - RW
2113
E1000_TDFHSE1000_TDFHS 0x03420 e1000_hw.h TX Data FIFO Head Saved - RW
2114
E1000_TDFTSE1000_TDFTS 0x03428 e1000_hw.h TX Data FIFO Tail Saved - RW
2115
E1000_TDFPCE1000_TDFPC 0x03430 e1000_hw.h TX Data FIFO Packet Count - RW
2116
E1000_TDBALE1000_TDBAL 0x03800 e1000_hw.h TX Descriptor Base Address Low - RW
2117
E1000_TDBAHE1000_TDBAH 0x03804 e1000_hw.h TX Descriptor Base Address High - RW
2118
E1000_TDLENE1000_TDLEN 0x03808 e1000_hw.h TX Descriptor Length - RW
2119
E1000_TDHE1000_TDH 0x03810 e1000_hw.h TX Descriptor Head - RW
2120
E1000_TDTE1000_TDT 0x03818 e1000_hw.h TX Descripotr Tail - RW
2121
E1000_TIDVE1000_TIDV 0x03820 e1000_hw.h TX Interrupt Delay Value - RW
2122
E1000_TXDCTLE1000_TXDCTL 0x03828 e1000_hw.h TX Descriptor Control - RW
2123
E1000_TADVE1000_TADV 0x0382C e1000_hw.h TX Interrupt Absolute Delay Val - RW
2124
E1000_TSPMTE1000_TSPMT 0x03830 e1000_hw.h TCP Segmentation PAD & Min Threshold - RW
2125
E1000_TARC0E1000_TARC0 0x03840 e1000_hw.h TX Arbitration Count (0)
2126
E1000_TDBAL1E1000_TDBAL1 0x03900 e1000_hw.h TX Desc Base Address Low (1) - RW
2127
E1000_TDBAH1E1000_TDBAH1 0x03904 e1000_hw.h TX Desc Base Address High (1) - RW
2128
E1000_TDLEN1E1000_TDLEN1 0x03908 e1000_hw.h TX Desc Length (1) - RW
2129
E1000_TDH1E1000_TDH1 0x03910 e1000_hw.h TX Desc Head (1) - RW
2130
E1000_TDT1E1000_TDT1 0x03918 e1000_hw.h TX Desc Tail (1) - RW
2131
E1000_TXDCTL1E1000_TXDCTL1 0x03928 e1000_hw.h TX Descriptor Control (1) - RW
2132
E1000_TARC1E1000_TARC1 0x03940 e1000_hw.h TX Arbitration Count (1)
2133
E1000_CRCERRSE1000_CRCERRS 0x04000 e1000_hw.h CRC Error Count - R/clr
2134
E1000_ALGNERRCE1000_ALGNERRC 0x04004 e1000_hw.h Alignment Error Count - R/clr
2135
E1000_SYMERRSE1000_SYMERRS 0x04008 e1000_hw.h Symbol Error Count - R/clr
2136
E1000_RXERRCE1000_RXERRC 0x0400C e1000_hw.h Receive Error Count - R/clr
2137
E1000_MPCE1000_MPC 0x04010 e1000_hw.h Missed Packet Count - R/clr
2138
E1000_SCCE1000_SCC 0x04014 e1000_hw.h Single Collision Count - R/clr
2139
E1000_ECOLE1000_ECOL 0x04018 e1000_hw.h Excessive Collision Count - R/clr
2140
E1000_MCCE1000_MCC 0x0401C e1000_hw.h Multiple Collision Count - R/clr
2141
E1000_LATECOLE1000_LATECOL 0x04020 e1000_hw.h Late Collision Count - R/clr
2142
E1000_COLCE1000_COLC 0x04028 e1000_hw.h Collision Count - R/clr
2143
E1000_DCE1000_DC 0x04030 e1000_hw.h Defer Count - R/clr
2144
E1000_TNCRSE1000_TNCRS 0x04034 e1000_hw.h TX-No CRS - R/clr
2145
E1000_SECE1000_SEC 0x04038 e1000_hw.h Sequence Error Count - R/clr
2146
E1000_CEXTERRE1000_CEXTERR 0x0403C e1000_hw.h Carrier Extension Error Count - R/clr
2147
E1000_RLECE1000_RLEC 0x04040 e1000_hw.h Receive Length Error Count - R/clr
2148
E1000_XONRXCE1000_XONRXC 0x04048 e1000_hw.h XON RX Count - R/clr
2149
E1000_XONTXCE1000_XONTXC 0x0404C e1000_hw.h XON TX Count - R/clr
2150
E1000_XOFFRXCE1000_XOFFRXC 0x04050 e1000_hw.h XOFF RX Count - R/clr
2151
E1000_XOFFTXCE1000_XOFFTXC 0x04054 e1000_hw.h XOFF TX Count - R/clr
2152
E1000_FCRUCE1000_FCRUC 0x04058 e1000_hw.h Flow Control RX Unsupported Count- R/clr
2153
E1000_PRC64E1000_PRC64 0x0405C e1000_hw.h Packets RX (64 bytes) - R/clr
2154
E1000_PRC127E1000_PRC127 0x04060 e1000_hw.h Packets RX (65-127 bytes) - R/clr
2155
E1000_PRC255E1000_PRC255 0x04064 e1000_hw.h Packets RX (128-255 bytes) - R/clr
2156
E1000_PRC511E1000_PRC511 0x04068 e1000_hw.h Packets RX (255-511 bytes) - R/clr
2157
E1000_PRC1023E1000_PRC1023 0x0406C e1000_hw.h Packets RX (512-1023 bytes) - R/clr
2158
E1000_PRC1522E1000_PRC1522 0x04070 e1000_hw.h Packets RX (1024-1522 bytes) - R/clr
2159
E1000_GPRCE1000_GPRC 0x04074 e1000_hw.h Good Packets RX Count - R/clr
2160
E1000_BPRCE1000_BPRC 0x04078 e1000_hw.h Broadcast Packets RX Count - R/clr
2161
E1000_MPRCE1000_MPRC 0x0407C e1000_hw.h Multicast Packets RX Count - R/clr
2162
E1000_GPTCE1000_GPTC 0x04080 e1000_hw.h Good Packets TX Count - R/clr
2163
E1000_GORCLE1000_GORCL 0x04088 e1000_hw.h Good Octets RX Count Low - R/clr
2164
E1000_GORCHE1000_GORCH 0x0408C e1000_hw.h Good Octets RX Count High - R/clr
2165
E1000_GOTCLE1000_GOTCL 0x04090 e1000_hw.h Good Octets TX Count Low - R/clr
2166
E1000_GOTCHE1000_GOTCH 0x04094 e1000_hw.h Good Octets TX Count High - R/clr
2167
E1000_RNBCE1000_RNBC 0x040A0 e1000_hw.h RX No Buffers Count - R/clr
2168
E1000_RUCE1000_RUC 0x040A4 e1000_hw.h RX Undersize Count - R/clr
2169
E1000_RFCE1000_RFC 0x040A8 e1000_hw.h RX Fragment Count - R/clr
2170
E1000_ROCE1000_ROC 0x040AC e1000_hw.h RX Oversize Count - R/clr
2171
E1000_RJCE1000_RJC 0x040B0 e1000_hw.h RX Jabber Count - R/clr
2172
E1000_MGTPRCE1000_MGTPRC 0x040B4 e1000_hw.h Management Packets RX Count - R/clr
2173
E1000_MGTPDCE1000_MGTPDC 0x040B8 e1000_hw.h Management Packets Dropped Count - R/clr
2174
E1000_MGTPTCE1000_MGTPTC 0x040BC e1000_hw.h Management Packets TX Count - R/clr
2175
E1000_TORLE1000_TORL 0x040C0 e1000_hw.h Total Octets RX Low - R/clr
2176
E1000_TORHE1000_TORH 0x040C4 e1000_hw.h Total Octets RX High - R/clr
2177
E1000_TOTLE1000_TOTL 0x040C8 e1000_hw.h Total Octets TX Low - R/clr
2178
E1000_TOTHE1000_TOTH 0x040CC e1000_hw.h Total Octets TX High - R/clr
2179
E1000_TPRE1000_TPR 0x040D0 e1000_hw.h Total Packets RX - R/clr
2180
E1000_TPTE1000_TPT 0x040D4 e1000_hw.h Total Packets TX - R/clr
2181
E1000_PTC64E1000_PTC64 0x040D8 e1000_hw.h Packets TX (64 bytes) - R/clr
2182
E1000_PTC127E1000_PTC127 0x040DC e1000_hw.h Packets TX (65-127 bytes) - R/clr
2183
E1000_PTC255E1000_PTC255 0x040E0 e1000_hw.h Packets TX (128-255 bytes) - R/clr
2184
E1000_PTC511E1000_PTC511 0x040E4 e1000_hw.h Packets TX (256-511 bytes) - R/clr
2185
E1000_PTC1023E1000_PTC1023 0x040E8 e1000_hw.h Packets TX (512-1023 bytes) - R/clr
2186
E1000_PTC1522E1000_PTC1522 0x040EC e1000_hw.h Packets TX (1024-1522 Bytes) - R/clr
2187
E1000_MPTCE1000_MPTC 0x040F0 e1000_hw.h Multicast Packets TX Count - R/clr
2188
E1000_BPTCE1000_BPTC 0x040F4 e1000_hw.h Broadcast Packets TX Count - R/clr
2189
E1000_TSCTCE1000_TSCTC 0x040F8 e1000_hw.h TCP Segmentation Context TX - R/clr
2190
E1000_TSCTFCE1000_TSCTFC 0x040FC e1000_hw.h TCP Segmentation Context TX Fail - R/clr
2191
E1000_IACE1000_IAC 0x04100 e1000_hw.h Interrupt Assertion Count
2192
E1000_ICRXPTCE1000_ICRXPTC 0x04104 e1000_hw.h Interrupt Cause Rx Packet Timer Expire Count
2193
E1000_ICRXATCE1000_ICRXATC 0x04108 e1000_hw.h Interrupt Cause Rx Absolute Timer Expire Count
2194
E1000_ICTXPTCE1000_ICTXPTC 0x0410C e1000_hw.h Interrupt Cause Tx Packet Timer Expire Count
2195
E1000_ICTXATCE1000_ICTXATC 0x04110 e1000_hw.h Interrupt Cause Tx Absolute Timer Expire Count
2196
E1000_ICTXQECE1000_ICTXQEC 0x04118 e1000_hw.h Interrupt Cause Tx Queue Empty Count
2197
E1000_ICTXQMTCE1000_ICTXQMTC 0x0411C e1000_hw.h Interrupt Cause Tx Queue Minimum Threshold Count
2198
E1000_ICRXDMTCE1000_ICRXDMTC 0x04120 e1000_hw.h Interrupt Cause Rx Descriptor Minimum Threshold Count
2199
E1000_ICRXOCE1000_ICRXOC 0x04124 e1000_hw.h Interrupt Cause Receiver Overrun Count
2200
E1000_RXCSUME1000_RXCSUM 0x05000 e1000_hw.h RX Checksum Control - RW
2201
E1000_RFCTLE1000_RFCTL 0x05008 e1000_hw.h Receive Filter Control
2202
E1000_MTAE1000_MTA 0x05200 e1000_hw.h Multicast Table Array - RW Array
2203
E1000_RAE1000_RA 0x05400 e1000_hw.h Receive Address - RW Array
2204
E1000_VFTAE1000_VFTA 0x05600 e1000_hw.h VLAN Filter Table Array - RW Array
2205
E1000_WUCE1000_WUC 0x05800 e1000_hw.h Wakeup Control - RW
2206
E1000_WUFCE1000_WUFC 0x05808 e1000_hw.h Wakeup Filter Control - RW
2207
E1000_WUSE1000_WUS 0x05810 e1000_hw.h Wakeup Status - RO
2208
E1000_MANCE1000_MANC 0x05820 e1000_hw.h Management Control - RW
2209
E1000_IPAVE1000_IPAV 0x05838 e1000_hw.h IP Address Valid - RW
2210
E1000_IP4ATE1000_IP4AT 0x05840 e1000_hw.h IPv4 Address Table - RW Array
2211
E1000_IP6ATE1000_IP6AT 0x05880 e1000_hw.h IPv6 Address Table - RW Array
2212
E1000_WUPLE1000_WUPL 0x05900 e1000_hw.h Wakeup Packet Length - RW
2213
E1000_WUPME1000_WUPM 0x05A00 e1000_hw.h Wakeup Packet Memory - RO A
2214
E1000_FFLTE1000_FFLT 0x05F00 e1000_hw.h Flexible Filter Length Table - RW Array
2215
E1000_HOST_IFE1000_HOST_IF 0x08800 e1000_hw.h Host Interface
2216
E1000_FFMTE1000_FFMT 0x09000 e1000_hw.h Flexible Filter Mask Table - RW Array
2217
E1000_FFVTE1000_FFVT 0x09800 e1000_hw.h Flexible Filter Value Table - RW Array
2218
E1000_KUMCTRLSTAE1000_KUMCTRLSTA 0x00034 e1000_hw.h MAC-PHY interface - RW
2219
E1000_MDPHYAE1000_MDPHYA 0x0003C e1000_hw.h PHY address - RW
2220
E1000_MANC2HE1000_MANC2H 0x05860 e1000_hw.h Managment Control To Host - RW
2221
E1000_SW_FW_SYNCE1000_SW_FW_SYNC 0x05B5C e1000_hw.h Software-Firmware Synchronization - RW
2222
E1000_GCRE1000_GCR 0x05B00 e1000_hw.h PCI-Ex Control
2223
E1000_GSCL_1E1000_GSCL_1 0x05B10 e1000_hw.h PCI-Ex Statistic Control #1
2224
E1000_GSCL_2E1000_GSCL_2 0x05B14 e1000_hw.h PCI-Ex Statistic Control #2
2225
E1000_GSCL_3E1000_GSCL_3 0x05B18 e1000_hw.h PCI-Ex Statistic Control #3
2226
E1000_GSCL_4E1000_GSCL_4 0x05B1C e1000_hw.h PCI-Ex Statistic Control #4
2227
E1000_FACTPSE1000_FACTPS 0x05B30 e1000_hw.h Function Active and Power State to MNG
2228
E1000_SWSME1000_SWSM 0x05B50 e1000_hw.h SW Semaphore
2229
E1000_FWSME1000_FWSM 0x05B54 e1000_hw.h FW Semaphore
2230
E1000_FFLT_DBGE1000_FFLT_DBG 0x05F04 e1000_hw.h Debug Register
2231
E1000_HICRE1000_HICR 0x08F00 e1000_hw.h Host Inteface Control
2232
E1000_CPUVECE1000_CPUVEC 0x02C10 e1000_hw.h CPU Vector Register - RW
2233
E1000_MRQCE1000_MRQC 0x05818 e1000_hw.h Multiple Receive Control - RW
2234
E1000_RETAE1000_RETA 0x05C00 e1000_hw.h Redirection Table - RW Array
2235
E1000_RSSRKE1000_RSSRK 0x05C80 e1000_hw.h RSS Random Key - RW Array
2236
E1000_RSSIME1000_RSSIM 0x05864 e1000_hw.h RSS Interrupt Mask
2237
E1000_RSSIRE1000_RSSIR 0x05868 e1000_hw.h RSS Interrupt Request
2238
E1000_82542_CTRLE1000_82542_CTRL E1000_CTRL e1000_hw.h  
2239
E1000_82542_CTRL_DUPE1000_82542_CTRL_DUP E1000_CTRL_DUP e1000_hw.h  
2240
E1000_82542_STATUSE1000_82542_STATUS E1000_STATUS e1000_hw.h  
2241
E1000_82542_EECDE1000_82542_EECD E1000_EECD e1000_hw.h  
2242
E1000_82542_EERDE1000_82542_EERD E1000_EERD e1000_hw.h  
2243
E1000_82542_CTRL_EXTE1000_82542_CTRL_EXT E1000_CTRL_EXT e1000_hw.h  
2244
E1000_82542_FLAE1000_82542_FLA E1000_FLA e1000_hw.h  
2245
E1000_82542_MDICE1000_82542_MDIC E1000_MDIC e1000_hw.h  
2246
E1000_82542_SCTLE1000_82542_SCTL E1000_SCTL e1000_hw.h  
2247
E1000_82542_FEXTNVME1000_82542_FEXTNVM E1000_FEXTNVM e1000_hw.h  
2248
E1000_82542_FCALE1000_82542_FCAL E1000_FCAL e1000_hw.h  
2249
E1000_82542_FCAHE1000_82542_FCAH E1000_FCAH e1000_hw.h  
2250
E1000_82542_FCTE1000_82542_FCT E1000_FCT e1000_hw.h  
2251
E1000_82542_VETE1000_82542_VET E1000_VET e1000_hw.h  
2252
E1000_82542_RAE1000_82542_RA 0x00040 e1000_hw.h  
2253
E1000_82542_ICRE1000_82542_ICR E1000_ICR e1000_hw.h  
2254
E1000_82542_ITRE1000_82542_ITR E1000_ITR e1000_hw.h  
2255
E1000_82542_ICSE1000_82542_ICS E1000_ICS e1000_hw.h  
2256
E1000_82542_IMSE1000_82542_IMS E1000_IMS e1000_hw.h  
2257
E1000_82542_IMCE1000_82542_IMC E1000_IMC e1000_hw.h  
2258
E1000_82542_RCTLE1000_82542_RCTL E1000_RCTL e1000_hw.h  
2259
E1000_82542_RDTRE1000_82542_RDTR 0x00108 e1000_hw.h  
2260
E1000_82542_RDBALE1000_82542_RDBAL 0x00110 e1000_hw.h  
2261
E1000_82542_RDBAHE1000_82542_RDBAH 0x00114 e1000_hw.h  
2262
E1000_82542_RDLENE1000_82542_RDLEN 0x00118 e1000_hw.h  
2263
E1000_82542_RDHE1000_82542_RDH 0x00120 e1000_hw.h  
2264
E1000_82542_RDTE1000_82542_RDT 0x00128 e1000_hw.h  
2265
E1000_82542_RDTR0E1000_82542_RDTR0 E1000_82542_RDTR e1000_hw.h  
2266
E1000_82542_RDBAL0E1000_82542_RDBAL0 E1000_82542_RDBAL e1000_hw.h  
2267
E1000_82542_RDBAH0E1000_82542_RDBAH0 E1000_82542_RDBAH e1000_hw.h  
2268
E1000_82542_RDLEN0E1000_82542_RDLEN0 E1000_82542_RDLEN e1000_hw.h  
2269
E1000_82542_RDH0E1000_82542_RDH0 E1000_82542_RDH e1000_hw.h  
2270
E1000_82542_RDT0E1000_82542_RDT0 E1000_82542_RDT e1000_hw.h  
2271
E1000_82542_RDBAH3E1000_82542_RDBAH3 0x02B04 e1000_hw.h RX Desc Base High Queue 3 - RW
2272
E1000_82542_RDBAL3E1000_82542_RDBAL3 0x02B00 e1000_hw.h RX Desc Low Queue 3 - RW
2273
E1000_82542_RDLEN3E1000_82542_RDLEN3 0x02B08 e1000_hw.h RX Desc Length Queue 3 - RW
2274
E1000_82542_RDH3E1000_82542_RDH3 0x02B10 e1000_hw.h RX Desc Head Queue 3 - RW
2275
E1000_82542_RDT3E1000_82542_RDT3 0x02B18 e1000_hw.h RX Desc Tail Queue 3 - RW
2276
E1000_82542_RDBAL2E1000_82542_RDBAL2 0x02A00 e1000_hw.h RX Desc Base Low Queue 2 - RW
2277
E1000_82542_RDBAH2E1000_82542_RDBAH2 0x02A04 e1000_hw.h RX Desc Base High Queue 2 - RW
2278
E1000_82542_RDLEN2E1000_82542_RDLEN2 0x02A08 e1000_hw.h RX Desc Length Queue 2 - RW
2279
E1000_82542_RDH2E1000_82542_RDH2 0x02A10 e1000_hw.h RX Desc Head Queue 2 - RW
2280
E1000_82542_RDT2E1000_82542_RDT2 0x02A18 e1000_hw.h RX Desc Tail Queue 2 - RW
2281
E1000_82542_RDTR1E1000_82542_RDTR1 0x00130 e1000_hw.h  
2282
E1000_82542_RDBAL1E1000_82542_RDBAL1 0x00138 e1000_hw.h  
2283
E1000_82542_RDBAH1E1000_82542_RDBAH1 0x0013C e1000_hw.h  
2284
E1000_82542_RDLEN1E1000_82542_RDLEN1 0x00140 e1000_hw.h  
2285
E1000_82542_RDH1E1000_82542_RDH1 0x00148 e1000_hw.h  
2286
E1000_82542_RDT1E1000_82542_RDT1 0x00150 e1000_hw.h  
2287
E1000_82542_FCRTHE1000_82542_FCRTH 0x00160 e1000_hw.h  
2288
E1000_82542_FCRTLE1000_82542_FCRTL 0x00168 e1000_hw.h  
2289
E1000_82542_FCTTVE1000_82542_FCTTV E1000_FCTTV e1000_hw.h  
2290
E1000_82542_TXCWE1000_82542_TXCW E1000_TXCW e1000_hw.h  
2291
E1000_82542_RXCWE1000_82542_RXCW E1000_RXCW e1000_hw.h  
2292
E1000_82542_MTAE1000_82542_MTA 0x00200 e1000_hw.h  
2293
E1000_82542_TCTLE1000_82542_TCTL E1000_TCTL e1000_hw.h  
2294
E1000_82542_TCTL_EXTE1000_82542_TCTL_EXT E1000_TCTL_EXT e1000_hw.h  
2295
E1000_82542_TIPGE1000_82542_TIPG E1000_TIPG e1000_hw.h  
2296
E1000_82542_TDBALE1000_82542_TDBAL 0x00420 e1000_hw.h  
2297
E1000_82542_TDBAHE1000_82542_TDBAH 0x00424 e1000_hw.h  
2298
E1000_82542_TDLENE1000_82542_TDLEN 0x00428 e1000_hw.h  
2299
E1000_82542_TDHE1000_82542_TDH 0x00430 e1000_hw.h  
2300
E1000_82542_TDTE1000_82542_TDT 0x00438 e1000_hw.h  
2301
E1000_82542_TIDVE1000_82542_TIDV 0x00440 e1000_hw.h  
2302
E1000_82542_TBTE1000_82542_TBT E1000_TBT e1000_hw.h  
2303
E1000_82542_AITE1000_82542_AIT E1000_AIT e1000_hw.h  
2304
E1000_82542_VFTAE1000_82542_VFTA 0x00600 e1000_hw.h  
2305
E1000_82542_LEDCTLE1000_82542_LEDCTL E1000_LEDCTL e1000_hw.h  
2306
E1000_82542_PBAE1000_82542_PBA E1000_PBA e1000_hw.h  
2307
E1000_82542_PBSE1000_82542_PBS E1000_PBS e1000_hw.h  
2308
E1000_82542_EEMNGCTLE1000_82542_EEMNGCTL E1000_EEMNGCTL e1000_hw.h  
2309
E1000_82542_EEARBCE1000_82542_EEARBC E1000_EEARBC e1000_hw.h  
2310
E1000_82542_FLASHTE1000_82542_FLASHT E1000_FLASHT e1000_hw.h  
2311
E1000_82542_EEWRE1000_82542_EEWR E1000_EEWR e1000_hw.h  
2312
E1000_82542_FLSWCTLE1000_82542_FLSWCTL E1000_FLSWCTL e1000_hw.h  
2313
E1000_82542_FLSWDATAE1000_82542_FLSWDATA E1000_FLSWDATA e1000_hw.h  
2314
E1000_82542_FLSWCNTE1000_82542_FLSWCNT E1000_FLSWCNT e1000_hw.h  
2315
E1000_82542_FLOPE1000_82542_FLOP E1000_FLOP e1000_hw.h  
2316
E1000_82542_EXTCNF_CTRLE1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL e1000_hw.h  
2317
E1000_82542_EXTCNF_SIZEE1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE e1000_hw.h  
2318
E1000_82542_PHY_CTRLE1000_82542_PHY_CTRL E1000_PHY_CTRL e1000_hw.h  
2319
E1000_82542_ERTE1000_82542_ERT E1000_ERT e1000_hw.h  
2320
E1000_82542_RXDCTLE1000_82542_RXDCTL E1000_RXDCTL e1000_hw.h  
2321
E1000_82542_RXDCTL1E1000_82542_RXDCTL1 E1000_RXDCTL1 e1000_hw.h  
2322
E1000_82542_RADVE1000_82542_RADV E1000_RADV e1000_hw.h  
2323
E1000_82542_RSRPDE1000_82542_RSRPD E1000_RSRPD e1000_hw.h  
2324
E1000_82542_TXDMACE1000_82542_TXDMAC E1000_TXDMAC e1000_hw.h  
2325
E1000_82542_KABGTXDE1000_82542_KABGTXD E1000_KABGTXD e1000_hw.h  
2326
E1000_82542_TDFHSE1000_82542_TDFHS E1000_TDFHS e1000_hw.h  
2327
E1000_82542_TDFTSE1000_82542_TDFTS E1000_TDFTS e1000_hw.h  
2328
E1000_82542_TDFPCE1000_82542_TDFPC E1000_TDFPC e1000_hw.h  
2329
E1000_82542_TXDCTLE1000_82542_TXDCTL E1000_TXDCTL e1000_hw.h  
2330
E1000_82542_TADVE1000_82542_TADV E1000_TADV e1000_hw.h  
2331
E1000_82542_TSPMTE1000_82542_TSPMT E1000_TSPMT e1000_hw.h  
2332
E1000_82542_CRCERRSE1000_82542_CRCERRS E1000_CRCERRS e1000_hw.h  
2333
E1000_82542_ALGNERRCE1000_82542_ALGNERRC E1000_ALGNERRC e1000_hw.h  
2334
E1000_82542_SYMERRSE1000_82542_SYMERRS E1000_SYMERRS e1000_hw.h  
2335
E1000_82542_RXERRCE1000_82542_RXERRC E1000_RXERRC e1000_hw.h  
2336
E1000_82542_MPCE1000_82542_MPC E1000_MPC e1000_hw.h  
2337
E1000_82542_SCCE1000_82542_SCC E1000_SCC e1000_hw.h  
2338
E1000_82542_ECOLE1000_82542_ECOL E1000_ECOL e1000_hw.h  
2339
E1000_82542_MCCE1000_82542_MCC E1000_MCC e1000_hw.h  
2340
E1000_82542_LATECOLE1000_82542_LATECOL E1000_LATECOL e1000_hw.h  
2341
E1000_82542_COLCE1000_82542_COLC E1000_COLC e1000_hw.h  
2342
E1000_82542_DCE1000_82542_DC E1000_DC e1000_hw.h  
2343
E1000_82542_TNCRSE1000_82542_TNCRS E1000_TNCRS e1000_hw.h  
2344
E1000_82542_SECE1000_82542_SEC E1000_SEC e1000_hw.h  
2345
E1000_82542_CEXTERRE1000_82542_CEXTERR E1000_CEXTERR e1000_hw.h  
2346
E1000_82542_RLECE1000_82542_RLEC E1000_RLEC e1000_hw.h  
2347
E1000_82542_XONRXCE1000_82542_XONRXC E1000_XONRXC e1000_hw.h  
2348
E1000_82542_XONTXCE1000_82542_XONTXC E1000_XONTXC e1000_hw.h  
2349
E1000_82542_XOFFRXCE1000_82542_XOFFRXC E1000_XOFFRXC e1000_hw.h  
2350
E1000_82542_XOFFTXCE1000_82542_XOFFTXC E1000_XOFFTXC e1000_hw.h  
2351
E1000_82542_FCRUCE1000_82542_FCRUC E1000_FCRUC e1000_hw.h  
2352
E1000_82542_PRC64E1000_82542_PRC64 E1000_PRC64 e1000_hw.h  
2353
E1000_82542_PRC127E1000_82542_PRC127 E1000_PRC127 e1000_hw.h  
2354
E1000_82542_PRC255E1000_82542_PRC255 E1000_PRC255 e1000_hw.h  
2355
E1000_82542_PRC511E1000_82542_PRC511 E1000_PRC511 e1000_hw.h  
2356
E1000_82542_PRC1023E1000_82542_PRC1023 E1000_PRC1023 e1000_hw.h  
2357
E1000_82542_PRC1522E1000_82542_PRC1522 E1000_PRC1522 e1000_hw.h  
2358
E1000_82542_GPRCE1000_82542_GPRC E1000_GPRC e1000_hw.h  
2359
E1000_82542_BPRCE1000_82542_BPRC E1000_BPRC e1000_hw.h  
2360
E1000_82542_MPRCE1000_82542_MPRC E1000_MPRC e1000_hw.h  
2361
E1000_82542_GPTCE1000_82542_GPTC E1000_GPTC e1000_hw.h  
2362
E1000_82542_GORCLE1000_82542_GORCL E1000_GORCL e1000_hw.h  
2363
E1000_82542_GORCHE1000_82542_GORCH E1000_GORCH e1000_hw.h  
2364
E1000_82542_GOTCLE1000_82542_GOTCL E1000_GOTCL e1000_hw.h  
2365
E1000_82542_GOTCHE1000_82542_GOTCH E1000_GOTCH e1000_hw.h  
2366
E1000_82542_RNBCE1000_82542_RNBC E1000_RNBC e1000_hw.h  
2367
E1000_82542_RUCE1000_82542_RUC E1000_RUC e1000_hw.h  
2368
E1000_82542_RFCE1000_82542_RFC E1000_RFC e1000_hw.h  
2369
E1000_82542_ROCE1000_82542_ROC E1000_ROC e1000_hw.h  
2370
E1000_82542_RJCE1000_82542_RJC E1000_RJC e1000_hw.h  
2371
E1000_82542_MGTPRCE1000_82542_MGTPRC E1000_MGTPRC e1000_hw.h  
2372
E1000_82542_MGTPDCE1000_82542_MGTPDC E1000_MGTPDC e1000_hw.h  
2373
E1000_82542_MGTPTCE1000_82542_MGTPTC E1000_MGTPTC e1000_hw.h  
2374
E1000_82542_TORLE1000_82542_TORL E1000_TORL e1000_hw.h  
2375
E1000_82542_TORHE1000_82542_TORH E1000_TORH e1000_hw.h  
2376
E1000_82542_TOTLE1000_82542_TOTL E1000_TOTL e1000_hw.h  
2377
E1000_82542_TOTHE1000_82542_TOTH E1000_TOTH e1000_hw.h  
2378
E1000_82542_TPRE1000_82542_TPR E1000_TPR e1000_hw.h  
2379
E1000_82542_TPTE1000_82542_TPT E1000_TPT e1000_hw.h  
2380
E1000_82542_PTC64E1000_82542_PTC64 E1000_PTC64 e1000_hw.h  
2381
E1000_82542_PTC127E1000_82542_PTC127 E1000_PTC127 e1000_hw.h  
2382
E1000_82542_PTC255E1000_82542_PTC255 E1000_PTC255 e1000_hw.h  
2383
E1000_82542_PTC511E1000_82542_PTC511 E1000_PTC511 e1000_hw.h  
2384
E1000_82542_PTC1023E1000_82542_PTC1023 E1000_PTC1023 e1000_hw.h  
2385
E1000_82542_PTC1522E1000_82542_PTC1522 E1000_PTC1522 e1000_hw.h  
2386
E1000_82542_MPTCE1000_82542_MPTC E1000_MPTC e1000_hw.h  
2387
E1000_82542_BPTCE1000_82542_BPTC E1000_BPTC e1000_hw.h  
2388
E1000_82542_TSCTCE1000_82542_TSCTC E1000_TSCTC e1000_hw.h  
2389
E1000_82542_TSCTFCE1000_82542_TSCTFC E1000_TSCTFC e1000_hw.h  
2390
E1000_82542_RXCSUME1000_82542_RXCSUM E1000_RXCSUM e1000_hw.h  
2391
E1000_82542_WUCE1000_82542_WUC E1000_WUC e1000_hw.h  
2392
E1000_82542_WUFCE1000_82542_WUFC E1000_WUFC e1000_hw.h  
2393
E1000_82542_WUSE1000_82542_WUS E1000_WUS e1000_hw.h  
2394
E1000_82542_MANCE1000_82542_MANC E1000_MANC e1000_hw.h  
2395
E1000_82542_IPAVE1000_82542_IPAV E1000_IPAV e1000_hw.h  
2396
E1000_82542_IP4ATE1000_82542_IP4AT E1000_IP4AT e1000_hw.h  
2397
E1000_82542_IP6ATE1000_82542_IP6AT E1000_IP6AT e1000_hw.h  
2398
E1000_82542_WUPLE1000_82542_WUPL E1000_WUPL e1000_hw.h  
2399
E1000_82542_WUPME1000_82542_WUPM E1000_WUPM e1000_hw.h  
2400
E1000_82542_FFLTE1000_82542_FFLT E1000_FFLT e1000_hw.h  
2401
E1000_82542_TDFHE1000_82542_TDFH 0x08010 e1000_hw.h  
2402
E1000_82542_TDFTE1000_82542_TDFT 0x08018 e1000_hw.h  
2403
E1000_82542_FFMTE1000_82542_FFMT E1000_FFMT e1000_hw.h  
2404
E1000_82542_FFVTE1000_82542_FFVT E1000_FFVT e1000_hw.h  
2405
E1000_82542_HOST_IFE1000_82542_HOST_IF E1000_HOST_IF e1000_hw.h  
2406
E1000_82542_IAME1000_82542_IAM E1000_IAM e1000_hw.h  
2407
E1000_82542_EEMNGCTLE1000_82542_EEMNGCTL E1000_EEMNGCTL e1000_hw.h  
2408
E1000_82542_PSRCTLE1000_82542_PSRCTL E1000_PSRCTL e1000_hw.h  
2409
E1000_82542_RAIDE1000_82542_RAID E1000_RAID e1000_hw.h  
2410
E1000_82542_TARC0E1000_82542_TARC0 E1000_TARC0 e1000_hw.h  
2411
E1000_82542_TDBAL1E1000_82542_TDBAL1 E1000_TDBAL1 e1000_hw.h  
2412
E1000_82542_TDBAH1E1000_82542_TDBAH1 E1000_TDBAH1 e1000_hw.h  
2413
E1000_82542_TDLEN1E1000_82542_TDLEN1 E1000_TDLEN1 e1000_hw.h  
2414
E1000_82542_TDH1E1000_82542_TDH1 E1000_TDH1 e1000_hw.h  
2415
E1000_82542_TDT1E1000_82542_TDT1 E1000_TDT1 e1000_hw.h  
2416
E1000_82542_TXDCTL1E1000_82542_TXDCTL1 E1000_TXDCTL1 e1000_hw.h  
2417
E1000_82542_TARC1E1000_82542_TARC1 E1000_TARC1 e1000_hw.h  
2418
E1000_82542_RFCTLE1000_82542_RFCTL E1000_RFCTL e1000_hw.h  
2419
E1000_82542_GCRE1000_82542_GCR E1000_GCR e1000_hw.h  
2420
E1000_82542_GSCL_1E1000_82542_GSCL_1 E1000_GSCL_1 e1000_hw.h  
2421
E1000_82542_GSCL_2E1000_82542_GSCL_2 E1000_GSCL_2 e1000_hw.h  
2422
E1000_82542_GSCL_3E1000_82542_GSCL_3 E1000_GSCL_3 e1000_hw.h  
2423
E1000_82542_GSCL_4E1000_82542_GSCL_4 E1000_GSCL_4 e1000_hw.h  
2424
E1000_82542_FACTPSE1000_82542_FACTPS E1000_FACTPS e1000_hw.h  
2425
E1000_82542_SWSME1000_82542_SWSM E1000_SWSM e1000_hw.h  
2426
E1000_82542_FWSME1000_82542_FWSM E1000_FWSM e1000_hw.h  
2427
E1000_82542_FFLT_DBGE1000_82542_FFLT_DBG E1000_FFLT_DBG e1000_hw.h  
2428
E1000_82542_IACE1000_82542_IAC E1000_IAC e1000_hw.h  
2429
E1000_82542_ICRXPTCE1000_82542_ICRXPTC E1000_ICRXPTC e1000_hw.h  
2430
E1000_82542_ICRXATCE1000_82542_ICRXATC E1000_ICRXATC e1000_hw.h  
2431
E1000_82542_ICTXPTCE1000_82542_ICTXPTC E1000_ICTXPTC e1000_hw.h  
2432
E1000_82542_ICTXATCE1000_82542_ICTXATC E1000_ICTXATC e1000_hw.h  
2433
E1000_82542_ICTXQECE1000_82542_ICTXQEC E1000_ICTXQEC e1000_hw.h  
2434
E1000_82542_ICTXQMTCE1000_82542_ICTXQMTC E1000_ICTXQMTC e1000_hw.h  
2435
E1000_82542_ICRXDMTCE1000_82542_ICRXDMTC E1000_ICRXDMTC e1000_hw.h  
2436
E1000_82542_ICRXOCE1000_82542_ICRXOC E1000_ICRXOC e1000_hw.h  
2437
E1000_82542_HICRE1000_82542_HICR E1000_HICR e1000_hw.h  
2438
E1000_82542_CPUVECE1000_82542_CPUVEC E1000_CPUVEC e1000_hw.h  
2439
E1000_82542_MRQCE1000_82542_MRQC E1000_MRQC e1000_hw.h  
2440
E1000_82542_RETAE1000_82542_RETA E1000_RETA e1000_hw.h  
2441
E1000_82542_RSSRKE1000_82542_RSSRK E1000_RSSRK e1000_hw.h  
2442
E1000_82542_RSSIME1000_82542_RSSIM E1000_RSSIM e1000_hw.h  
2443
E1000_82542_RSSIRE1000_82542_RSSIR E1000_RSSIR e1000_hw.h  
2444
E1000_82542_KUMCTRLSTAE1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA e1000_hw.h  
2445
E1000_82542_SW_FW_SYNCE1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC e1000_hw.h  
2446
E1000_82542_MANC2HE1000_82542_MANC2H E1000_MANC2H e1000_hw.h  
2447
E1000_EEPROM_SWDPIN0E1000_EEPROM_SWDPIN0 0x0001 e1000_hw.h SWDPIN 0 EEPROM Value
2448
E1000_EEPROM_LED_LOGICE1000_EEPROM_LED_LOGIC 0x0020 e1000_hw.h Led Logic Word
2449
E1000_EEPROM_RW_REG_DATAE1000_EEPROM_RW_REG_DATA 16 e1000_hw.h Offset to data in EEPROM read/write registers
2450
E1000_EEPROM_RW_REG_DONEE1000_EEPROM_RW_REG_DONE 2 e1000_hw.h Offset to READ/WRITE done bit
2451
E1000_EEPROM_RW_REG_STARTE1000_EEPROM_RW_REG_START 1 e1000_hw.h First bit for telling part to start operation
2452
E1000_EEPROM_RW_ADDR_SHIFTE1000_EEPROM_RW_ADDR_SHIFT 2 e1000_hw.h Shift to the address bits
2453
E1000_EEPROM_POLL_WRITEE1000_EEPROM_POLL_WRITE 1 e1000_hw.h Flag for polling for write complete
2454
E1000_EEPROM_POLL_READE1000_EEPROM_POLL_READ 0 e1000_hw.h Flag for polling for read complete
2455
E1000_CTRL_FDE1000_CTRL_FD 0x00000001 e1000_hw.h Full duplex.0=half; 1=full
2456
E1000_CTRL_BEME1000_CTRL_BEM 0x00000002 e1000_hw.h Endian Mode.0=little,1=big
2457
E1000_CTRL_PRIORE1000_CTRL_PRIOR 0x00000004 e1000_hw.h Priority on PCI. 0=rx,1=fair
2458
E1000_CTRL_GIO_MASTER_DISABLEE1000_CTRL_GIO_MASTER_DISABLE 0x00000004 e1000_hw.h Blocks new Master requests
2459
E1000_CTRL_LRSTE1000_CTRL_LRST 0x00000008 e1000_hw.h Link reset. 0=normal,1=reset
2460
E1000_CTRL_TMEE1000_CTRL_TME 0x00000010 e1000_hw.h Test mode. 0=normal,1=test
2461
E1000_CTRL_SLEE1000_CTRL_SLE 0x00000020 e1000_hw.h Serial Link on 0=dis,1=en
2462
E1000_CTRL_ASDEE1000_CTRL_ASDE 0x00000020 e1000_hw.h Auto-speed detect enable
2463
E1000_CTRL_SLUE1000_CTRL_SLU 0x00000040 e1000_hw.h Set link up (Force Link)
2464
E1000_CTRL_ILOSE1000_CTRL_ILOS 0x00000080 e1000_hw.h Invert Loss-Of Signal
2465
E1000_CTRL_SPD_SELE1000_CTRL_SPD_SEL 0x00000300 e1000_hw.h Speed Select Mask
2466
E1000_CTRL_SPD_10E1000_CTRL_SPD_10 0x00000000 e1000_hw.h Force 10Mb
2467
E1000_CTRL_SPD_100E1000_CTRL_SPD_100 0x00000100 e1000_hw.h Force 100Mb
2468
E1000_CTRL_SPD_1000E1000_CTRL_SPD_1000 0x00000200 e1000_hw.h Force 1Gb
2469
E1000_CTRL_BEM32E1000_CTRL_BEM32 0x00000400 e1000_hw.h Big Endian 32 mode
2470
E1000_CTRL_FRCSPDE1000_CTRL_FRCSPD 0x00000800 e1000_hw.h Force Speed
2471
E1000_CTRL_FRCDPXE1000_CTRL_FRCDPX 0x00001000 e1000_hw.h Force Duplex
2472
E1000_CTRL_D_UD_ENE1000_CTRL_D_UD_EN 0x00002000 e1000_hw.h Dock/Undock enable
2473
E1000_CTRL_D_UD_POLARITYE1000_CTRL_D_UD_POLARITY 0x00004000 e1000_hw.h Defined polarity of Dock/Undock indication in SDP[0]
2474
E1000_CTRL_FORCE_PHY_RESETE1000_CTRL_FORCE_PHY_RESET 0x00008000 e1000_hw.h Reset both PHY ports, through PHYRST_N pin
2475
E1000_CTRL_EXT_LINK_ENE1000_CTRL_EXT_LINK_EN 0x00010000 e1000_hw.h enable link status from external LINK_0 and LINK_1 pins
2476
E1000_CTRL_SWDPIN0E1000_CTRL_SWDPIN0 0x00040000 e1000_hw.h SWDPIN 0 value
2477
E1000_CTRL_SWDPIN1E1000_CTRL_SWDPIN1 0x00080000 e1000_hw.h SWDPIN 1 value
2478
E1000_CTRL_SWDPIN2E1000_CTRL_SWDPIN2 0x00100000 e1000_hw.h SWDPIN 2 value
2479
E1000_CTRL_SWDPIN3E1000_CTRL_SWDPIN3 0x00200000 e1000_hw.h SWDPIN 3 value
2480
E1000_CTRL_SWDPIO0E1000_CTRL_SWDPIO0 0x00400000 e1000_hw.h SWDPIN 0 Input or output
2481
E1000_CTRL_SWDPIO1E1000_CTRL_SWDPIO1 0x00800000 e1000_hw.h SWDPIN 1 input or output
2482
E1000_CTRL_SWDPIO2E1000_CTRL_SWDPIO2 0x01000000 e1000_hw.h SWDPIN 2 input or output
2483
E1000_CTRL_SWDPIO3E1000_CTRL_SWDPIO3 0x02000000 e1000_hw.h SWDPIN 3 input or output
2484
E1000_CTRL_RSTE1000_CTRL_RST 0x04000000 e1000_hw.h Global reset
2485
E1000_CTRL_RFCEE1000_CTRL_RFCE 0x08000000 e1000_hw.h Receive Flow Control enable
2486
E1000_CTRL_TFCEE1000_CTRL_TFCE 0x10000000 e1000_hw.h Transmit flow control enable
2487
E1000_CTRL_RTEE1000_CTRL_RTE 0x20000000 e1000_hw.h Routing tag enable
2488
E1000_CTRL_VMEE1000_CTRL_VME 0x40000000 e1000_hw.h IEEE VLAN mode enable
2489
E1000_CTRL_PHY_RSTE1000_CTRL_PHY_RST 0x80000000 e1000_hw.h PHY Reset
2490
E1000_CTRL_SW2FW_INTE1000_CTRL_SW2FW_INT 0x02000000 e1000_hw.h Initiate an interrupt to manageability engine
2491
E1000_STATUS_FDE1000_STATUS_FD 0x00000001 e1000_hw.h Full duplex.0=half,1=full
2492
E1000_STATUS_LUE1000_STATUS_LU 0x00000002 e1000_hw.h Link up.0=no,1=link
2493
E1000_STATUS_FUNC_MASKE1000_STATUS_FUNC_MASK 0x0000000C e1000_hw.h PCI Function Mask
2494
E1000_STATUS_FUNC_SHIFTE1000_STATUS_FUNC_SHIFT 2 e1000_hw.h  
2495
E1000_STATUS_FUNC_0E1000_STATUS_FUNC_0 0x00000000 e1000_hw.h Function 0
2496
E1000_STATUS_FUNC_1E1000_STATUS_FUNC_1 0x00000004 e1000_hw.h Function 1
2497
E1000_STATUS_TXOFFE1000_STATUS_TXOFF 0x00000010 e1000_hw.h transmission paused
2498
E1000_STATUS_TBIMODEE1000_STATUS_TBIMODE 0x00000020 e1000_hw.h TBI mode
2499
E1000_STATUS_SPEED_MASKE1000_STATUS_SPEED_MASK 0x000000C0 e1000_hw.h  
2500
E1000_STATUS_SPEED_10E1000_STATUS_SPEED_10 0x00000000 e1000_hw.h Speed 10Mb/s
2501
E1000_STATUS_SPEED_100E1000_STATUS_SPEED_100 0x00000040 e1000_hw.h Speed 100Mb/s
2502
E1000_STATUS_SPEED_1000E1000_STATUS_SPEED_1000 0x00000080 e1000_hw.h Speed 1000Mb/s
2503
E1000_STATUS_LAN_INIT_DONEE1000_STATUS_LAN_INIT_DONE 0x00000200 e1000_hw.h Lan Init Completion
2504
E1000_STATUS_ASDVE1000_STATUS_ASDV 0x00000300 e1000_hw.h Auto speed detect value
2505
E1000_STATUS_DOCK_CIE1000_STATUS_DOCK_CI 0x00000800 e1000_hw.h Change in Dock/Undock state. Clear on write '0'.
2506
E1000_STATUS_GIO_MASTER_ENABLEE1000_STATUS_GIO_MASTER_ENABLE 0x00080000 e1000_hw.h Status of Master requests.
2507
E1000_STATUS_MTXCKOKE1000_STATUS_MTXCKOK 0x00000400 e1000_hw.h MTX clock running OK
2508
E1000_STATUS_PCI66E1000_STATUS_PCI66 0x00000800 e1000_hw.h In 66Mhz slot
2509
E1000_STATUS_BUS64E1000_STATUS_BUS64 0x00001000 e1000_hw.h In 64 bit slot
2510
E1000_STATUS_PCIX_MODEE1000_STATUS_PCIX_MODE 0x00002000 e1000_hw.h PCI-X mode
2511
E1000_STATUS_PCIX_SPEEDE1000_STATUS_PCIX_SPEED 0x0000C000 e1000_hw.h PCI-X bus speed
2512
E1000_STATUS_BMC_SKU_0E1000_STATUS_BMC_SKU_0 0x00100000 e1000_hw.h BMC USB redirect disabled
2513
E1000_STATUS_BMC_SKU_1E1000_STATUS_BMC_SKU_1 0x00200000 e1000_hw.h BMC SRAM disabled
2514
E1000_STATUS_BMC_SKU_2E1000_STATUS_BMC_SKU_2 0x00400000 e1000_hw.h BMC SDRAM disabled
2515
E1000_STATUS_BMC_CRYPTOE1000_STATUS_BMC_CRYPTO 0x00800000 e1000_hw.h BMC crypto disabled
2516
E1000_STATUS_BMC_LITEE1000_STATUS_BMC_LITE 0x01000000 e1000_hw.h BMC external code execution disabled
2517
E1000_STATUS_RGMII_ENABLEE1000_STATUS_RGMII_ENABLE 0x02000000 e1000_hw.h RGMII disabled
2518
E1000_STATUS_FUSE_8E1000_STATUS_FUSE_8 0x04000000 e1000_hw.h  
2519
E1000_STATUS_FUSE_9E1000_STATUS_FUSE_9 0x08000000 e1000_hw.h  
2520
E1000_STATUS_SERDES0_DISE1000_STATUS_SERDES0_DIS 0x10000000 e1000_hw.h SERDES disabled on port 0
2521
E1000_STATUS_SERDES1_DISE1000_STATUS_SERDES1_DIS 0x20000000 e1000_hw.h SERDES disabled on port 1
2522
E1000_STATUS_PCIX_SPEED_66E1000_STATUS_PCIX_SPEED_66 0x00000000 e1000_hw.h PCI-X bus speed 50-66 MHz
2523
E1000_STATUS_PCIX_SPEED_100E1000_STATUS_PCIX_SPEED_100 0x00004000 e1000_hw.h PCI-X bus speed 66-100 MHz
2524
E1000_STATUS_PCIX_SPEED_133E1000_STATUS_PCIX_SPEED_133 0x00008000 e1000_hw.h PCI-X bus speed 100-133 MHz
2525
E1000_EECD_SKE1000_EECD_SK 0x00000001 e1000_hw.h EEPROM Clock
2526
E1000_EECD_CSE1000_EECD_CS 0x00000002 e1000_hw.h EEPROM Chip Select
2527
E1000_EECD_DIE1000_EECD_DI 0x00000004 e1000_hw.h EEPROM Data In
2528
E1000_EECD_DOE1000_EECD_DO 0x00000008 e1000_hw.h EEPROM Data Out
2529
E1000_EECD_FWE_MASKE1000_EECD_FWE_MASK 0x00000030 e1000_hw.h  
2530
E1000_EECD_FWE_DISE1000_EECD_FWE_DIS 0x00000010 e1000_hw.h Disable FLASH writes
2531
E1000_EECD_FWE_ENE1000_EECD_FWE_EN 0x00000020 e1000_hw.h Enable FLASH writes
2532
E1000_EECD_FWE_SHIFTE1000_EECD_FWE_SHIFT 4 e1000_hw.h  
2533
E1000_EECD_REQE1000_EECD_REQ 0x00000040 e1000_hw.h EEPROM Access Request
2534
E1000_EECD_GNTE1000_EECD_GNT 0x00000080 e1000_hw.h EEPROM Access Grant
2535
E1000_EECD_PRESE1000_EECD_PRES 0x00000100 e1000_hw.h EEPROM Present
2536
E1000_EECD_SIZEE1000_EECD_SIZE 0x00000200 e1000_hw.h EEPROM Size (0=64 word 1=256 word)
2537
E1000_EECD_ADDR_BITSE1000_EECD_ADDR_BITS 0x00000400 e1000_hw.h EEPROM Addressing bits based on type
2538
E1000_EECD_TYPEE1000_EECD_TYPE 0x00002000 e1000_hw.h EEPROM Type (1-SPI, 0-Microwire)
2539
E1000_EEPROM_GRANT_ATTEMPTSE1000_EEPROM_GRANT_ATTEMPTS 1000 e1000_hw.h EEPROM # attempts to gain grant
2540
E1000_EECD_AUTO_RDE1000_EECD_AUTO_RD 0x00000200 e1000_hw.h EEPROM Auto Read done
2541
E1000_EECD_SIZE_EX_MASKE1000_EECD_SIZE_EX_MASK 0x00007800 e1000_hw.h EEprom Size
2542
E1000_EECD_SIZE_EX_SHIFTE1000_EECD_SIZE_EX_SHIFT 11 e1000_hw.h  
2543
E1000_EECD_NVADDSE1000_EECD_NVADDS 0x00018000 e1000_hw.h NVM Address Size
2544
E1000_EECD_SELSHADE1000_EECD_SELSHAD 0x00020000 e1000_hw.h Select Shadow RAM
2545
E1000_EECD_INITSRAME1000_EECD_INITSRAM 0x00040000 e1000_hw.h Initialize Shadow RAM
2546
E1000_EECD_FLUPDE1000_EECD_FLUPD 0x00080000 e1000_hw.h Update FLASH
2547
E1000_EECD_AUPDENE1000_EECD_AUPDEN 0x00100000 e1000_hw.h Enable Autonomous FLASH update
2548
E1000_EECD_SHADVE1000_EECD_SHADV 0x00200000 e1000_hw.h Shadow RAM Data Valid
2549
E1000_EECD_SEC1VALE1000_EECD_SEC1VAL 0x00400000 e1000_hw.h Sector One Valid
2550
E1000_EECD_SECVAL_SHIFTE1000_EECD_SECVAL_SHIFT 22 e1000_hw.h  
2551
E1000_STM_OPCODEE1000_STM_OPCODE 0xDB00 e1000_hw.h  
2552
E1000_HICR_FW_RESETE1000_HICR_FW_RESET 0xC0 e1000_hw.h  
2553
E1000_SHADOW_RAM_WORDSE1000_SHADOW_RAM_WORDS 2048 e1000_hw.h  
2554
E1000_ICH_NVM_SIG_WORDE1000_ICH_NVM_SIG_WORD 0x13 e1000_hw.h  
2555
E1000_ICH_NVM_SIG_MASKE1000_ICH_NVM_SIG_MASK 0xC0 e1000_hw.h  
2556
E1000_EERD_STARTE1000_EERD_START 0x00000001 e1000_hw.h Start Read
2557
E1000_EERD_DONEE1000_EERD_DONE 0x00000010 e1000_hw.h Read Done
2558
E1000_EERD_ADDR_SHIFTE1000_EERD_ADDR_SHIFT 8 e1000_hw.h  
2559
E1000_EERD_ADDR_MASKE1000_EERD_ADDR_MASK 0x0000FF00 e1000_hw.h Read Address
2560
E1000_EERD_DATA_SHIFTE1000_EERD_DATA_SHIFT 16 e1000_hw.h  
2561
E1000_EERD_DATA_MASKE1000_EERD_DATA_MASK 0xFFFF0000 e1000_hw.h Read Data
2562
EEPROM_STATUS_RDY_SPIEEPROM_STATUS_RDY_SPI 0x01 e1000_hw.h  
2563
EEPROM_STATUS_WEN_SPIEEPROM_STATUS_WEN_SPI 0x02 e1000_hw.h  
2564
EEPROM_STATUS_BP0_SPIEEPROM_STATUS_BP0_SPI 0x04 e1000_hw.h  
2565
EEPROM_STATUS_BP1_SPIEEPROM_STATUS_BP1_SPI 0x08 e1000_hw.h  
2566
EEPROM_STATUS_WPEN_SPIEEPROM_STATUS_WPEN_SPI 0x80 e1000_hw.h  
2567
E1000_CTRL_EXT_GPI0_ENE1000_CTRL_EXT_GPI0_EN 0x00000001 e1000_hw.h Maps SDP4 to GPI0
2568
E1000_CTRL_EXT_GPI1_ENE1000_CTRL_EXT_GPI1_EN 0x00000002 e1000_hw.h Maps SDP5 to GPI1
2569
E1000_CTRL_EXT_PHYINT_ENE1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN e1000_hw.h  
2570
E1000_CTRL_EXT_GPI2_ENE1000_CTRL_EXT_GPI2_EN 0x00000004 e1000_hw.h Maps SDP6 to GPI2
2571
E1000_CTRL_EXT_GPI3_ENE1000_CTRL_EXT_GPI3_EN 0x00000008 e1000_hw.h Maps SDP7 to GPI3
2572
E1000_CTRL_EXT_SDP4_DATAE1000_CTRL_EXT_SDP4_DATA 0x00000010 e1000_hw.h Value of SW Defineable Pin 4
2573
E1000_CTRL_EXT_SDP5_DATAE1000_CTRL_EXT_SDP5_DATA 0x00000020 e1000_hw.h Value of SW Defineable Pin 5
2574
E1000_CTRL_EXT_PHY_INTE1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA e1000_hw.h  
2575
E1000_CTRL_EXT_SDP6_DATAE1000_CTRL_EXT_SDP6_DATA 0x00000040 e1000_hw.h Value of SW Defineable Pin 6
2576
E1000_CTRL_EXT_SDP7_DATAE1000_CTRL_EXT_SDP7_DATA 0x00000080 e1000_hw.h Value of SW Defineable Pin 7
2577
E1000_CTRL_EXT_SDP4_DIRE1000_CTRL_EXT_SDP4_DIR 0x00000100 e1000_hw.h Direction of SDP4 0=in 1=out
2578
E1000_CTRL_EXT_SDP5_DIRE1000_CTRL_EXT_SDP5_DIR 0x00000200 e1000_hw.h Direction of SDP5 0=in 1=out
2579
E1000_CTRL_EXT_SDP6_DIRE1000_CTRL_EXT_SDP6_DIR 0x00000400 e1000_hw.h Direction of SDP6 0=in 1=out
2580
E1000_CTRL_EXT_SDP7_DIRE1000_CTRL_EXT_SDP7_DIR 0x00000800 e1000_hw.h Direction of SDP7 0=in 1=out
2581
E1000_CTRL_EXT_ASDCHKE1000_CTRL_EXT_ASDCHK 0x00001000 e1000_hw.h Initiate an ASD sequence
2582
E1000_CTRL_EXT_EE_RSTE1000_CTRL_EXT_EE_RST 0x00002000 e1000_hw.h Reinitialize from EEPROM
2583
E1000_CTRL_EXT_IPSE1000_CTRL_EXT_IPS 0x00004000 e1000_hw.h Invert Power State
2584
E1000_CTRL_EXT_SPD_BYPSE1000_CTRL_EXT_SPD_BYPS 0x00008000 e1000_hw.h Speed Select Bypass
2585
E1000_CTRL_EXT_RO_DISE1000_CTRL_EXT_RO_DIS 0x00020000 e1000_hw.h Relaxed Ordering disable
2586
E1000_CTRL_EXT_LINK_MODE_MASKE1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 e1000_hw.h  
2587
E1000_CTRL_EXT_LINK_MODE_GMIIE1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 e1000_hw.h  
2588
E1000_CTRL_EXT_LINK_MODE_TBIE1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 e1000_hw.h  
2589
E1000_CTRL_EXT_LINK_MODE_KMRNE1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 e1000_hw.h  
2590
E1000_CTRL_EXT_LINK_MODE_SERDESE1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000 e1000_hw.h  
2591
E1000_CTRL_EXT_LINK_MODE_SGMIIE1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 e1000_hw.h  
2592
E1000_CTRL_EXT_WR_WMARK_MASKE1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 e1000_hw.h  
2593
E1000_CTRL_EXT_WR_WMARK_256E1000_CTRL_EXT_WR_WMARK_256 0x00000000 e1000_hw.h  
2594
E1000_CTRL_EXT_WR_WMARK_320E1000_CTRL_EXT_WR_WMARK_320 0x01000000 e1000_hw.h  
2595
E1000_CTRL_EXT_WR_WMARK_384E1000_CTRL_EXT_WR_WMARK_384 0x02000000 e1000_hw.h  
2596
E1000_CTRL_EXT_WR_WMARK_448E1000_CTRL_EXT_WR_WMARK_448 0x03000000 e1000_hw.h  
2597
E1000_CTRL_EXT_DRV_LOADE1000_CTRL_EXT_DRV_LOAD 0x10000000 e1000_hw.h Driver loaded bit for FW
2598
E1000_CTRL_EXT_IAMEE1000_CTRL_EXT_IAME 0x08000000 e1000_hw.h Interrupt acknowledge Auto-mask
2599
E1000_CTRL_EXT_INT_TIMER_CLRE1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 e1000_hw.h Clear Interrupt timers after IMS clear
2600
E1000_CRTL_EXT_PB_PARENE1000_CRTL_EXT_PB_PAREN 0x01000000 e1000_hw.h packet buffer parity error detection enabled
2601
E1000_CTRL_EXT_DF_PARENE1000_CTRL_EXT_DF_PAREN 0x02000000 e1000_hw.h descriptor FIFO parity error detection enable
2602
E1000_CTRL_EXT_GHOST_PARENE1000_CTRL_EXT_GHOST_PAREN 0x40000000 e1000_hw.h  
2603
E1000_MDIC_DATA_MASKE1000_MDIC_DATA_MASK 0x0000FFFF e1000_hw.h  
2604
E1000_MDIC_REG_MASKE1000_MDIC_REG_MASK 0x001F0000 e1000_hw.h  
2605
E1000_MDIC_REG_SHIFTE1000_MDIC_REG_SHIFT 16 e1000_hw.h  
2606
E1000_MDIC_PHY_MASKE1000_MDIC_PHY_MASK 0x03E00000 e1000_hw.h  
2607
E1000_MDIC_PHY_SHIFTE1000_MDIC_PHY_SHIFT 21 e1000_hw.h  
2608
E1000_MDIC_OP_WRITEE1000_MDIC_OP_WRITE 0x04000000 e1000_hw.h  
2609
E1000_MDIC_OP_READE1000_MDIC_OP_READ 0x08000000 e1000_hw.h  
2610
E1000_MDIC_READYE1000_MDIC_READY 0x10000000 e1000_hw.h  
2611
E1000_MDIC_INT_ENE1000_MDIC_INT_EN 0x20000000 e1000_hw.h  
2612
E1000_MDIC_ERRORE1000_MDIC_ERROR 0x40000000 e1000_hw.h  
2613
E1000_KUMCTRLSTA_MASKE1000_KUMCTRLSTA_MASK 0x0000FFFF e1000_hw.h  
2614
E1000_KUMCTRLSTA_OFFSETE1000_KUMCTRLSTA_OFFSET 0x001F0000 e1000_hw.h  
2615
E1000_KUMCTRLSTA_OFFSET_SHIFTE1000_KUMCTRLSTA_OFFSET_SHIFT 16 e1000_hw.h  
2616
E1000_KUMCTRLSTA_RENE1000_KUMCTRLSTA_REN 0x00200000 e1000_hw.h  
2617
E1000_KUMCTRLSTA_OFFSET_FIFO_CTE1000_KUMCTRLSTA_OFFSET_FIFO_CT 0x00000000 e1000_hw.h  
2618
E1000_KUMCTRLSTA_OFFSET_CTRLE1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001 e1000_hw.h  
2619
E1000_KUMCTRLSTA_OFFSET_INB_CTRE1000_KUMCTRLSTA_OFFSET_INB_CTR 0x00000002 e1000_hw.h  
2620
E1000_KUMCTRLSTA_OFFSET_DIAGE1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003 e1000_hw.h  
2621
E1000_KUMCTRLSTA_OFFSET_TIMEOUTE1000_KUMCTRLSTA_OFFSET_TIMEOUT 0x00000004 e1000_hw.h  
2622
E1000_KUMCTRLSTA_OFFSET_INB_PARE1000_KUMCTRLSTA_OFFSET_INB_PAR 0x00000009 e1000_hw.h  
2623
E1000_KUMCTRLSTA_OFFSET_HD_CTRLE1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 e1000_hw.h  
2624
E1000_KUMCTRLSTA_OFFSET_M2P_SERE1000_KUMCTRLSTA_OFFSET_M2P_SER 0x0000001E e1000_hw.h  
2625
E1000_KUMCTRLSTA_OFFSET_M2P_MODE1000_KUMCTRLSTA_OFFSET_M2P_MOD 0x0000001F e1000_hw.h  
2626
E1000_KUMCTRLSTA_FIFO_CTRL_RX_BE1000_KUMCTRLSTA_FIFO_CTRL_RX_B 0x00000008 e1000_hw.h  
2627
E1000_KUMCTRLSTA_FIFO_CTRL_TX_BE1000_KUMCTRLSTA_FIFO_CTRL_TX_B 0x00000800 e1000_hw.h  
2628
E1000_KUMCTRLSTA_INB_CTRL_LINK_E1000_KUMCTRLSTA_INB_CTRL_LINK_ 0x00000500 e1000_hw.h  
2629
E1000_KUMCTRLSTA_INB_CTRL_DIS_PE1000_KUMCTRLSTA_INB_CTRL_DIS_P 0x00000010 e1000_hw.h  
2630
E1000_KUMCTRLSTA_HD_CTRL_10_100E1000_KUMCTRLSTA_HD_CTRL_10_100 0x00000004 e1000_hw.h  
2631
E1000_KUMCTRLSTA_HD_CTRL_1000_DE1000_KUMCTRLSTA_HD_CTRL_1000_D 0x00000000 e1000_hw.h  
2632
E1000_KUMCTRLSTA_OFFSET_K0S_CTRE1000_KUMCTRLSTA_OFFSET_K0S_CTR 0x0000001E e1000_hw.h  
2633
E1000_KUMCTRLSTA_DIAG_FELPBKE1000_KUMCTRLSTA_DIAG_FELPBK 0x2000 e1000_hw.h  
2634
E1000_KUMCTRLSTA_DIAG_NELPBKE1000_KUMCTRLSTA_DIAG_NELPBK 0x1000 e1000_hw.h  
2635
E1000_KUMCTRLSTA_K0S_100_ENE1000_KUMCTRLSTA_K0S_100_EN 0x2000 e1000_hw.h  
2636
E1000_KUMCTRLSTA_K0S_GBE_ENE1000_KUMCTRLSTA_K0S_GBE_EN 0x1000 e1000_hw.h  
2637
E1000_KUMCTRLSTA_K0S_ENTRY_LATEE1000_KUMCTRLSTA_K0S_ENTRY_LATE 0x0003 e1000_hw.h  
2638
E1000_KABGTXD_BGSQLBIASE1000_KABGTXD_BGSQLBIAS 0x00050000 e1000_hw.h  
2639
E1000_PHY_CTRL_SPD_ENE1000_PHY_CTRL_SPD_EN 0x00000001 e1000_hw.h  
2640
E1000_PHY_CTRL_D0A_LPLUE1000_PHY_CTRL_D0A_LPLU 0x00000002 e1000_hw.h  
2641
E1000_PHY_CTRL_NOND0A_LPLUE1000_PHY_CTRL_NOND0A_LPLU 0x00000004 e1000_hw.h  
2642
E1000_PHY_CTRL_NOND0A_GBE_DISABE1000_PHY_CTRL_NOND0A_GBE_DISAB 0x00000008 e1000_hw.h  
2643
E1000_PHY_CTRL_GBE_DISABLEE1000_PHY_CTRL_GBE_DISABLE 0x00000040 e1000_hw.h  
2644
E1000_PHY_CTRL_B2B_ENE1000_PHY_CTRL_B2B_EN 0x00000080 e1000_hw.h  
2645
E1000_LEDCTL_LED0_MODE_MASKE1000_LEDCTL_LED0_MODE_MASK 0x0000000F e1000_hw.h  
2646
E1000_LEDCTL_LED0_MODE_SHIFTE1000_LEDCTL_LED0_MODE_SHIFT 0 e1000_hw.h  
2647
E1000_LEDCTL_LED0_BLINK_RATEE1000_LEDCTL_LED0_BLINK_RATE 0x0000020 e1000_hw.h  
2648
E1000_LEDCTL_LED0_IVRTE1000_LEDCTL_LED0_IVRT 0x00000040 e1000_hw.h  
2649
E1000_LEDCTL_LED0_BLINKE1000_LEDCTL_LED0_BLINK 0x00000080 e1000_hw.h  
2650
E1000_LEDCTL_LED1_MODE_MASKE1000_LEDCTL_LED1_MODE_MASK 0x00000F00 e1000_hw.h  
2651
E1000_LEDCTL_LED1_MODE_SHIFTE1000_LEDCTL_LED1_MODE_SHIFT 8 e1000_hw.h  
2652
E1000_LEDCTL_LED1_BLINK_RATEE1000_LEDCTL_LED1_BLINK_RATE 0x0002000 e1000_hw.h  
2653
E1000_LEDCTL_LED1_IVRTE1000_LEDCTL_LED1_IVRT 0x00004000 e1000_hw.h  
2654
E1000_LEDCTL_LED1_BLINKE1000_LEDCTL_LED1_BLINK 0x00008000 e1000_hw.h  
2655
E1000_LEDCTL_LED2_MODE_MASKE1000_LEDCTL_LED2_MODE_MASK 0x000F0000 e1000_hw.h  
2656
E1000_LEDCTL_LED2_MODE_SHIFTE1000_LEDCTL_LED2_MODE_SHIFT 16 e1000_hw.h  
2657
E1000_LEDCTL_LED2_BLINK_RATEE1000_LEDCTL_LED2_BLINK_RATE 0x00200000 e1000_hw.h  
2658
E1000_LEDCTL_LED2_IVRTE1000_LEDCTL_LED2_IVRT 0x00400000 e1000_hw.h  
2659
E1000_LEDCTL_LED2_BLINKE1000_LEDCTL_LED2_BLINK 0x00800000 e1000_hw.h  
2660
E1000_LEDCTL_LED3_MODE_MASKE1000_LEDCTL_LED3_MODE_MASK 0x0F000000 e1000_hw.h  
2661
E1000_LEDCTL_LED3_MODE_SHIFTE1000_LEDCTL_LED3_MODE_SHIFT 24 e1000_hw.h  
2662
E1000_LEDCTL_LED3_BLINK_RATEE1000_LEDCTL_LED3_BLINK_RATE 0x20000000 e1000_hw.h  
2663
E1000_LEDCTL_LED3_IVRTE1000_LEDCTL_LED3_IVRT 0x40000000 e1000_hw.h  
2664
E1000_LEDCTL_LED3_BLINKE1000_LEDCTL_LED3_BLINK 0x80000000 e1000_hw.h  
2665
E1000_LEDCTL_MODE_LINK_10_1000E1000_LEDCTL_MODE_LINK_10_1000 0x0 e1000_hw.h  
2666
E1000_LEDCTL_MODE_LINK_100_1000E1000_LEDCTL_MODE_LINK_100_1000 0x1 e1000_hw.h  
2667
E1000_LEDCTL_MODE_LINK_UPE1000_LEDCTL_MODE_LINK_UP 0x2 e1000_hw.h  
2668
E1000_LEDCTL_MODE_ACTIVITYE1000_LEDCTL_MODE_ACTIVITY 0x3 e1000_hw.h  
2669
E1000_LEDCTL_MODE_LINK_ACTIVITYE1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 e1000_hw.h  
2670
E1000_LEDCTL_MODE_LINK_10E1000_LEDCTL_MODE_LINK_10 0x5 e1000_hw.h  
2671
E1000_LEDCTL_MODE_LINK_100E1000_LEDCTL_MODE_LINK_100 0x6 e1000_hw.h  
2672
E1000_LEDCTL_MODE_LINK_1000E1000_LEDCTL_MODE_LINK_1000 0x7 e1000_hw.h  
2673
E1000_LEDCTL_MODE_PCIX_MODEE1000_LEDCTL_MODE_PCIX_MODE 0x8 e1000_hw.h  
2674
E1000_LEDCTL_MODE_FULL_DUPLEXE1000_LEDCTL_MODE_FULL_DUPLEX 0x9 e1000_hw.h  
2675
E1000_LEDCTL_MODE_COLLISIONE1000_LEDCTL_MODE_COLLISION 0xA e1000_hw.h  
2676
E1000_LEDCTL_MODE_BUS_SPEEDE1000_LEDCTL_MODE_BUS_SPEED 0xB e1000_hw.h  
2677
E1000_LEDCTL_MODE_BUS_SIZEE1000_LEDCTL_MODE_BUS_SIZE 0xC e1000_hw.h  
2678
E1000_LEDCTL_MODE_PAUSEDE1000_LEDCTL_MODE_PAUSED 0xD e1000_hw.h  
2679
E1000_LEDCTL_MODE_LED_ONE1000_LEDCTL_MODE_LED_ON 0xE e1000_hw.h  
2680
E1000_LEDCTL_MODE_LED_OFFE1000_LEDCTL_MODE_LED_OFF 0xF e1000_hw.h  
2681
E1000_RAH_AVE1000_RAH_AV 0x80000000 e1000_hw.h Receive descriptor valid
2682
E1000_RAH_POOL_1E1000_RAH_POOL_1 0x00040000 e1000_hw.h  
2683
E1000_ICR_TXDWE1000_ICR_TXDW 0x00000001 e1000_hw.h Transmit desc written back
2684
E1000_ICR_TXQEE1000_ICR_TXQE 0x00000002 e1000_hw.h Transmit Queue empty
2685
E1000_ICR_LSCE1000_ICR_LSC 0x00000004 e1000_hw.h Link Status Change
2686
E1000_ICR_RXSEQE1000_ICR_RXSEQ 0x00000008 e1000_hw.h rx sequence error
2687
E1000_ICR_RXDMT0E1000_ICR_RXDMT0 0x00000010 e1000_hw.h rx desc min. threshold (0)
2688
E1000_ICR_DOUTSYNCE1000_ICR_DOUTSYNC 0x10000000 e1000_hw.h NIC DMA out of sync
2689
E1000_ICR_RXOE1000_ICR_RXO 0x00000040 e1000_hw.h rx overrun
2690
E1000_ICR_RXT0E1000_ICR_RXT0 0x00000080 e1000_hw.h rx timer intr (ring 0)
2691
E1000_ICR_MDACE1000_ICR_MDAC 0x00000200 e1000_hw.h MDIO access complete
2692
E1000_ICR_RXCFGE1000_ICR_RXCFG 0x00000400 e1000_hw.h RX /c/ ordered set
2693
E1000_ICR_GPI_EN0E1000_ICR_GPI_EN0 0x00000800 e1000_hw.h GP Int 0
2694
E1000_ICR_GPI_EN1E1000_ICR_GPI_EN1 0x00001000 e1000_hw.h GP Int 1
2695
E1000_ICR_GPI_EN2E1000_ICR_GPI_EN2 0x00002000 e1000_hw.h GP Int 2
2696
E1000_ICR_GPI_EN3E1000_ICR_GPI_EN3 0x00004000 e1000_hw.h GP Int 3
2697
E1000_ICR_TXD_LOWE1000_ICR_TXD_LOW 0x00008000 e1000_hw.h  
2698
E1000_ICR_SRPDE1000_ICR_SRPD 0x00010000 e1000_hw.h  
2699
E1000_ICR_ACKE1000_ICR_ACK 0x00020000 e1000_hw.h Receive Ack frame
2700
E1000_ICR_MNGE1000_ICR_MNG 0x00040000 e1000_hw.h Manageability event
2701
E1000_ICR_DOCKE1000_ICR_DOCK 0x00080000 e1000_hw.h Dock/Undock
2702
E1000_ICR_INT_ASSERTEDE1000_ICR_INT_ASSERTED 0x80000000 e1000_hw.h If this bit asserted, the driver should claim the interrupt
2703
E1000_ICR_RXD_FIFO_PAR0E1000_ICR_RXD_FIFO_PAR0 0x00100000 e1000_hw.h queue 0 Rx descriptor FIFO parity error
2704
E1000_ICR_TXD_FIFO_PAR0E1000_ICR_TXD_FIFO_PAR0 0x00200000 e1000_hw.h queue 0 Tx descriptor FIFO parity error
2705
E1000_ICR_HOST_ARB_PARE1000_ICR_HOST_ARB_PAR 0x00400000 e1000_hw.h host arb read buffer parity error
2706
E1000_ICR_PB_PARE1000_ICR_PB_PAR 0x00800000 e1000_hw.h packet buffer parity error
2707
E1000_ICR_RXD_FIFO_PAR1E1000_ICR_RXD_FIFO_PAR1 0x01000000 e1000_hw.h queue 1 Rx descriptor FIFO parity error
2708
E1000_ICR_TXD_FIFO_PAR1E1000_ICR_TXD_FIFO_PAR1 0x02000000 e1000_hw.h queue 1 Tx descriptor FIFO parity error
2709
E1000_ICR_ALL_PARITYE1000_ICR_ALL_PARITY 0x03F00000 e1000_hw.h all parity error bits
2710
E1000_ICR_DSWE1000_ICR_DSW 0x00000020 e1000_hw.h FW changed the status of DISSW bit in the FWSM
2711
E1000_ICR_PHYINTE1000_ICR_PHYINT 0x00001000 e1000_hw.h LAN connected device generates an interrupt
2712
E1000_ICR_EPRSTE1000_ICR_EPRST 0x00100000 e1000_hw.h ME handware reset occurs
2713
E1000_ICS_TXDWE1000_ICS_TXDW E1000_ICR_TXDW e1000_hw.h Transmit desc written back
2714
E1000_ICS_TXQEE1000_ICS_TXQE E1000_ICR_TXQE e1000_hw.h Transmit Queue empty
2715
E1000_ICS_LSCE1000_ICS_LSC E1000_ICR_LSC e1000_hw.h Link Status Change
2716
E1000_ICS_RXSEQE1000_ICS_RXSEQ E1000_ICR_RXSEQ e1000_hw.h rx sequence error
2717
E1000_ICS_RXDMT0E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 e1000_hw.h rx desc min. threshold
2718
E1000_ICS_RXOE1000_ICS_RXO E1000_ICR_RXO e1000_hw.h rx overrun
2719
E1000_ICS_RXT0E1000_ICS_RXT0 E1000_ICR_RXT0 e1000_hw.h rx timer intr
2720
E1000_ICS_MDACE1000_ICS_MDAC E1000_ICR_MDAC e1000_hw.h MDIO access complete
2721
E1000_ICS_RXCFGE1000_ICS_RXCFG E1000_ICR_RXCFG e1000_hw.h RX /c/ ordered set
2722
E1000_ICS_GPI_EN0E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 e1000_hw.h GP Int 0
2723
E1000_ICS_GPI_EN1E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 e1000_hw.h GP Int 1
2724
E1000_ICS_GPI_EN2E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 e1000_hw.h GP Int 2
2725
E1000_ICS_GPI_EN3E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 e1000_hw.h GP Int 3
2726
E1000_ICS_TXD_LOWE1000_ICS_TXD_LOW E1000_ICR_TXD_LOW e1000_hw.h  
2727
E1000_ICS_SRPDE1000_ICS_SRPD E1000_ICR_SRPD e1000_hw.h  
2728
E1000_ICS_ACKE1000_ICS_ACK E1000_ICR_ACK e1000_hw.h Receive Ack frame
2729
E1000_ICS_MNGE1000_ICS_MNG E1000_ICR_MNG e1000_hw.h Manageability event
2730
E1000_ICS_DOCKE1000_ICS_DOCK E1000_ICR_DOCK e1000_hw.h Dock/Undock
2731
E1000_ICS_RXD_FIFO_PAR0E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000_hw.h queue 0 Rx descriptor FIFO parity error
2732
E1000_ICS_TXD_FIFO_PAR0E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000_hw.h queue 0 Tx descriptor FIFO parity error
2733
E1000_ICS_HOST_ARB_PARE1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000_hw.h host arb read buffer parity error
2734
E1000_ICS_PB_PARE1000_ICS_PB_PAR E1000_ICR_PB_PAR e1000_hw.h packet buffer parity error
2735
E1000_ICS_RXD_FIFO_PAR1E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000_hw.h queue 1 Rx descriptor FIFO parity error
2736
E1000_ICS_TXD_FIFO_PAR1E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000_hw.h queue 1 Tx descriptor FIFO parity error
2737
E1000_ICS_DSWE1000_ICS_DSW E1000_ICR_DSW e1000_hw.h  
2738
E1000_ICS_PHYINTE1000_ICS_PHYINT E1000_ICR_PHYINT e1000_hw.h  
2739
E1000_ICS_EPRSTE1000_ICS_EPRST E1000_ICR_EPRST e1000_hw.h  
2740
E1000_IMS_TXDWE1000_IMS_TXDW E1000_ICR_TXDW e1000_hw.h Transmit desc written back
2741
E1000_IMS_TXQEE1000_IMS_TXQE E1000_ICR_TXQE e1000_hw.h Transmit Queue empty
2742
E1000_IMS_LSCE1000_IMS_LSC E1000_ICR_LSC e1000_hw.h Link Status Change
2743
E1000_IMS_RXSEQE1000_IMS_RXSEQ E1000_ICR_RXSEQ e1000_hw.h rx sequence error
2744
E1000_IMS_RXDMT0E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 e1000_hw.h rx desc min. threshold
2745
E1000_IMS_RXOE1000_IMS_RXO E1000_ICR_RXO e1000_hw.h rx overrun
2746
E1000_IMS_DOUTSYNCE1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC e1000_hw.h NIC DMA out of sync
2747
E1000_IMS_RXT0E1000_IMS_RXT0 E1000_ICR_RXT0 e1000_hw.h rx timer intr
2748
E1000_IMS_MDACE1000_IMS_MDAC E1000_ICR_MDAC e1000_hw.h MDIO access complete
2749
E1000_IMS_RXCFGE1000_IMS_RXCFG E1000_ICR_RXCFG e1000_hw.h RX /c/ ordered set
2750
E1000_IMS_GPI_EN0E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 e1000_hw.h GP Int 0
2751
E1000_IMS_GPI_EN1E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 e1000_hw.h GP Int 1
2752
E1000_IMS_GPI_EN2E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 e1000_hw.h GP Int 2
2753
E1000_IMS_GPI_EN3E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 e1000_hw.h GP Int 3
2754
E1000_IMS_TXD_LOWE1000_IMS_TXD_LOW E1000_ICR_TXD_LOW e1000_hw.h  
2755
E1000_IMS_SRPDE1000_IMS_SRPD E1000_ICR_SRPD e1000_hw.h  
2756
E1000_IMS_ACKE1000_IMS_ACK E1000_ICR_ACK e1000_hw.h Receive Ack frame
2757
E1000_IMS_MNGE1000_IMS_MNG E1000_ICR_MNG e1000_hw.h Manageability event
2758
E1000_IMS_DOCKE1000_IMS_DOCK E1000_ICR_DOCK e1000_hw.h Dock/Undock
2759
E1000_IMS_RXD_FIFO_PAR0E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000_hw.h queue 0 Rx descriptor FIFO parity error
2760
E1000_IMS_TXD_FIFO_PAR0E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000_hw.h queue 0 Tx descriptor FIFO parity error
2761
E1000_IMS_HOST_ARB_PARE1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000_hw.h host arb read buffer parity error
2762
E1000_IMS_PB_PARE1000_IMS_PB_PAR E1000_ICR_PB_PAR e1000_hw.h packet buffer parity error
2763
E1000_IMS_RXD_FIFO_PAR1E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000_hw.h queue 1 Rx descriptor FIFO parity error
2764
E1000_IMS_TXD_FIFO_PAR1E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000_hw.h queue 1 Tx descriptor FIFO parity error
2765
E1000_IMS_DSWE1000_IMS_DSW E1000_ICR_DSW e1000_hw.h  
2766
E1000_IMS_PHYINTE1000_IMS_PHYINT E1000_ICR_PHYINT e1000_hw.h  
2767
E1000_IMS_EPRSTE1000_IMS_EPRST E1000_ICR_EPRST e1000_hw.h  
2768
E1000_IMC_TXDWE1000_IMC_TXDW E1000_ICR_TXDW e1000_hw.h Transmit desc written back
2769
E1000_IMC_TXQEE1000_IMC_TXQE E1000_ICR_TXQE e1000_hw.h Transmit Queue empty
2770
E1000_IMC_LSCE1000_IMC_LSC E1000_ICR_LSC e1000_hw.h Link Status Change
2771
E1000_IMC_RXSEQE1000_IMC_RXSEQ E1000_ICR_RXSEQ e1000_hw.h rx sequence error
2772
E1000_IMC_RXDMT0E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 e1000_hw.h rx desc min. threshold
2773
E1000_IMC_RXOE1000_IMC_RXO E1000_ICR_RXO e1000_hw.h rx overrun
2774
E1000_IMC_RXT0E1000_IMC_RXT0 E1000_ICR_RXT0 e1000_hw.h rx timer intr
2775
E1000_IMC_MDACE1000_IMC_MDAC E1000_ICR_MDAC e1000_hw.h MDIO access complete
2776
E1000_IMC_RXCFGE1000_IMC_RXCFG E1000_ICR_RXCFG e1000_hw.h RX /c/ ordered set
2777
E1000_IMC_GPI_EN0E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 e1000_hw.h GP Int 0
2778
E1000_IMC_GPI_EN1E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 e1000_hw.h GP Int 1
2779
E1000_IMC_GPI_EN2E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 e1000_hw.h GP Int 2
2780
E1000_IMC_GPI_EN3E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 e1000_hw.h GP Int 3
2781
E1000_IMC_TXD_LOWE1000_IMC_TXD_LOW E1000_ICR_TXD_LOW e1000_hw.h  
2782
E1000_IMC_SRPDE1000_IMC_SRPD E1000_ICR_SRPD e1000_hw.h  
2783
E1000_IMC_ACKE1000_IMC_ACK E1000_ICR_ACK e1000_hw.h Receive Ack frame
2784
E1000_IMC_MNGE1000_IMC_MNG E1000_ICR_MNG e1000_hw.h Manageability event
2785
E1000_IMC_DOCKE1000_IMC_DOCK E1000_ICR_DOCK e1000_hw.h Dock/Undock
2786
E1000_IMC_RXD_FIFO_PAR0E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000_hw.h queue 0 Rx descriptor FIFO parity error
2787
E1000_IMC_TXD_FIFO_PAR0E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000_hw.h queue 0 Tx descriptor FIFO parity error
2788
E1000_IMC_HOST_ARB_PARE1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000_hw.h host arb read buffer parity error
2789
E1000_IMC_PB_PARE1000_IMC_PB_PAR E1000_ICR_PB_PAR e1000_hw.h packet buffer parity error
2790
E1000_IMC_RXD_FIFO_PAR1E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000_hw.h queue 1 Rx descriptor FIFO parity error
2791
E1000_IMC_TXD_FIFO_PAR1E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000_hw.h queue 1 Tx descriptor FIFO parity error
2792
E1000_IMC_DSWE1000_IMC_DSW E1000_ICR_DSW e1000_hw.h  
2793
E1000_IMC_PHYINTE1000_IMC_PHYINT E1000_ICR_PHYINT e1000_hw.h  
2794
E1000_IMC_EPRSTE1000_IMC_EPRST E1000_ICR_EPRST e1000_hw.h  
2795
E1000_RCTL_RSTE1000_RCTL_RST 0x00000001 e1000_hw.h Software reset
2796
E1000_RCTL_ENE1000_RCTL_EN 0x00000002 e1000_hw.h enable
2797
E1000_RCTL_SBPE1000_RCTL_SBP 0x00000004 e1000_hw.h store bad packet
2798
E1000_RCTL_UPEE1000_RCTL_UPE 0x00000008 e1000_hw.h unicast promiscuous enable
2799
E1000_RCTL_MPEE1000_RCTL_MPE 0x00000010 e1000_hw.h multicast promiscuous enab
2800
E1000_RCTL_LPEE1000_RCTL_LPE 0x00000020 e1000_hw.h long packet enable
2801
E1000_RCTL_LBM_NOE1000_RCTL_LBM_NO 0x00000000 e1000_hw.h no loopback mode
2802
E1000_RCTL_LBM_MACE1000_RCTL_LBM_MAC 0x00000040 e1000_hw.h MAC loopback mode
2803
E1000_RCTL_LBM_SLPE1000_RCTL_LBM_SLP 0x00000080 e1000_hw.h serial link loopback mode
2804
E1000_RCTL_LBM_TCVRE1000_RCTL_LBM_TCVR 0x000000C0 e1000_hw.h tcvr loopback mode
2805
E1000_RCTL_DTYP_MASKE1000_RCTL_DTYP_MASK 0x00000C00 e1000_hw.h Descriptor type mask
2806
E1000_RCTL_DTYP_PSE1000_RCTL_DTYP_PS 0x00000400 e1000_hw.h Packet Split descriptor
2807
E1000_RCTL_RDMTS_HALFE1000_RCTL_RDMTS_HALF 0x00000000 e1000_hw.h rx desc min threshold size
2808
E1000_RCTL_RDMTS_QUATE1000_RCTL_RDMTS_QUAT 0x00000100 e1000_hw.h rx desc min threshold size
2809
E1000_RCTL_RDMTS_EIGTHE1000_RCTL_RDMTS_EIGTH 0x00000200 e1000_hw.h rx desc min threshold size
2810
E1000_RCTL_MO_SHIFTE1000_RCTL_MO_SHIFT 12 e1000_hw.h multicast offset shift
2811
E1000_RCTL_MO_0E1000_RCTL_MO_0 0x00000000 e1000_hw.h multicast offset 11:0
2812
E1000_RCTL_MO_1E1000_RCTL_MO_1 0x00001000 e1000_hw.h multicast offset 12:1
2813
E1000_RCTL_MO_2E1000_RCTL_MO_2 0x00002000 e1000_hw.h multicast offset 13:2
2814
E1000_RCTL_MO_3E1000_RCTL_MO_3 0x00003000 e1000_hw.h multicast offset 15:4
2815
E1000_RCTL_MDRE1000_RCTL_MDR 0x00004000 e1000_hw.h multicast desc ring 0
2816
E1000_RCTL_BAME1000_RCTL_BAM 0x00008000 e1000_hw.h broadcast enable
2817
E1000_RCTL_SZ_2048E1000_RCTL_SZ_2048 0x00000000 e1000_hw.h rx buffer size 2048
2818
E1000_RCTL_SZ_1024E1000_RCTL_SZ_1024 0x00010000 e1000_hw.h rx buffer size 1024
2819
E1000_RCTL_SZ_512E1000_RCTL_SZ_512 0x00020000 e1000_hw.h rx buffer size 512
2820
E1000_RCTL_SZ_256E1000_RCTL_SZ_256 0x00030000 e1000_hw.h rx buffer size 256
2821
E1000_RCTL_SZ_16384E1000_RCTL_SZ_16384 0x00010000 e1000_hw.h rx buffer size 16384
2822
E1000_RCTL_SZ_8192E1000_RCTL_SZ_8192 0x00020000 e1000_hw.h rx buffer size 8192
2823
E1000_RCTL_SZ_4096E1000_RCTL_SZ_4096 0x00030000 e1000_hw.h rx buffer size 4096
2824
E1000_RCTL_VFEE1000_RCTL_VFE 0x00040000 e1000_hw.h vlan filter enable
2825
E1000_RCTL_CFIENE1000_RCTL_CFIEN 0x00080000 e1000_hw.h canonical form enable
2826
E1000_RCTL_CFIE1000_RCTL_CFI 0x00100000 e1000_hw.h canonical form indicator
2827
E1000_RCTL_DPFE1000_RCTL_DPF 0x00400000 e1000_hw.h discard pause frames
2828
E1000_RCTL_PMCFE1000_RCTL_PMCF 0x00800000 e1000_hw.h pass MAC control frames
2829
E1000_RCTL_BSEXE1000_RCTL_BSEX 0x02000000 e1000_hw.h Buffer size extension
2830
E1000_RCTL_SECRCE1000_RCTL_SECRC 0x04000000 e1000_hw.h Strip Ethernet CRC
2831
E1000_RCTL_FLXBUF_MASKE1000_RCTL_FLXBUF_MASK 0x78000000 e1000_hw.h Flexible buffer size
2832
E1000_RCTL_FLXBUF_SHIFTE1000_RCTL_FLXBUF_SHIFT 27 e1000_hw.h Flexible buffer shift
2833
E1000_PSRCTL_BSIZE0_MASKE1000_PSRCTL_BSIZE0_MASK 0x0000007F e1000_hw.h  
2834
E1000_PSRCTL_BSIZE1_MASKE1000_PSRCTL_BSIZE1_MASK 0x00003F00 e1000_hw.h  
2835
E1000_PSRCTL_BSIZE2_MASKE1000_PSRCTL_BSIZE2_MASK 0x003F0000 e1000_hw.h  
2836
E1000_PSRCTL_BSIZE3_MASKE1000_PSRCTL_BSIZE3_MASK 0x3F000000 e1000_hw.h  
2837
E1000_PSRCTL_BSIZE0_SHIFTE1000_PSRCTL_BSIZE0_SHIFT 7 e1000_hw.h Shift _right_ 7
2838
E1000_PSRCTL_BSIZE1_SHIFTE1000_PSRCTL_BSIZE1_SHIFT 2 e1000_hw.h Shift _right_ 2
2839
E1000_PSRCTL_BSIZE2_SHIFTE1000_PSRCTL_BSIZE2_SHIFT 6 e1000_hw.h Shift _left_ 6
2840
E1000_PSRCTL_BSIZE3_SHIFTE1000_PSRCTL_BSIZE3_SHIFT 14 e1000_hw.h Shift _left_ 14
2841
E1000_SWFW_EEP_SME1000_SWFW_EEP_SM 0x0001 e1000_hw.h  
2842
E1000_SWFW_PHY0_SME1000_SWFW_PHY0_SM 0x0002 e1000_hw.h  
2843
E1000_SWFW_PHY1_SME1000_SWFW_PHY1_SM 0x0004 e1000_hw.h  
2844
E1000_SWFW_MAC_CSR_SME1000_SWFW_MAC_CSR_SM 0x0008 e1000_hw.h  
2845
E1000_RDT_DELAYE1000_RDT_DELAY 0x0000ffff e1000_hw.h Delay timer (1=1024us)
2846
E1000_RDT_FPDBE1000_RDT_FPDB 0x80000000 e1000_hw.h Flush descriptor block
2847
E1000_RDLEN_LENE1000_RDLEN_LEN 0x0007ff80 e1000_hw.h descriptor length
2848
E1000_RDH_RDHE1000_RDH_RDH 0x0000ffff e1000_hw.h receive descriptor head
2849
E1000_RDT_RDTE1000_RDT_RDT 0x0000ffff e1000_hw.h receive descriptor tail
2850
E1000_FCRTH_RTHE1000_FCRTH_RTH 0x0000FFF8 e1000_hw.h Mask Bits[15:3] for RTH
2851
E1000_FCRTH_XFCEE1000_FCRTH_XFCE 0x80000000 e1000_hw.h External Flow Control Enable
2852
E1000_FCRTL_RTLE1000_FCRTL_RTL 0x0000FFF8 e1000_hw.h Mask Bits[15:3] for RTL
2853
E1000_FCRTL_XONEE1000_FCRTL_XONE 0x80000000 e1000_hw.h Enable XON frame transmission
2854
E1000_RFCTL_ISCSI_DISE1000_RFCTL_ISCSI_DIS 0x00000001 e1000_hw.h  
2855
E1000_RFCTL_ISCSI_DWC_MASKE1000_RFCTL_ISCSI_DWC_MASK 0x0000003E e1000_hw.h  
2856
E1000_RFCTL_ISCSI_DWC_SHIFTE1000_RFCTL_ISCSI_DWC_SHIFT 1 e1000_hw.h  
2857
E1000_RFCTL_NFSW_DISE1000_RFCTL_NFSW_DIS 0x00000040 e1000_hw.h  
2858
E1000_RFCTL_NFSR_DISE1000_RFCTL_NFSR_DIS 0x00000080 e1000_hw.h  
2859
E1000_RFCTL_NFS_VER_MASKE1000_RFCTL_NFS_VER_MASK 0x00000300 e1000_hw.h  
2860
E1000_RFCTL_NFS_VER_SHIFTE1000_RFCTL_NFS_VER_SHIFT 8 e1000_hw.h  
2861
E1000_RFCTL_IPV6_DISE1000_RFCTL_IPV6_DIS 0x00000400 e1000_hw.h  
2862
E1000_RFCTL_IPV6_XSUM_DISE1000_RFCTL_IPV6_XSUM_DIS 0x00000800 e1000_hw.h  
2863
E1000_RFCTL_ACK_DISE1000_RFCTL_ACK_DIS 0x00001000 e1000_hw.h  
2864
E1000_RFCTL_ACKD_DISE1000_RFCTL_ACKD_DIS 0x00002000 e1000_hw.h  
2865
E1000_RFCTL_IPFRSP_DISE1000_RFCTL_IPFRSP_DIS 0x00004000 e1000_hw.h  
2866
E1000_RFCTL_EXTENE1000_RFCTL_EXTEN 0x00008000 e1000_hw.h  
2867
E1000_RFCTL_IPV6_EX_DISE1000_RFCTL_IPV6_EX_DIS 0x00010000 e1000_hw.h  
2868
E1000_RFCTL_NEW_IPV6_EXT_DISE1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 e1000_hw.h  
2869
E1000_RXDCTL_PTHRESHE1000_RXDCTL_PTHRESH 0x0000003F e1000_hw.h RXDCTL Prefetch Threshold
2870
E1000_RXDCTL_HTHRESHE1000_RXDCTL_HTHRESH 0x00003F00 e1000_hw.h RXDCTL Host Threshold
2871
E1000_RXDCTL_WTHRESHE1000_RXDCTL_WTHRESH 0x003F0000 e1000_hw.h RXDCTL Writeback Threshold
2872
E1000_RXDCTL_GRANE1000_RXDCTL_GRAN 0x01000000 e1000_hw.h RXDCTL Granularity
2873
E1000_RXDCTL_QUEUE_ENABLEE1000_RXDCTL_QUEUE_ENABLE 0x02000000 e1000_hw.h Enable specific Rx Queue
2874
IGB_RX_PTHRESHIGB_RX_PTHRESH 16 e1000_hw.h  
2875
IGB_RX_HTHRESHIGB_RX_HTHRESH 8 e1000_hw.h  
2876
IGB_RX_WTHRESHIGB_RX_WTHRESH 1 e1000_hw.h  
2877
E1000_TXDCTL_PTHRESHE1000_TXDCTL_PTHRESH 0x0000003F e1000_hw.h TXDCTL Prefetch Threshold
2878
E1000_TXDCTL_HTHRESHE1000_TXDCTL_HTHRESH 0x00003F00 e1000_hw.h TXDCTL Host Threshold
2879
E1000_TXDCTL_WTHRESHE1000_TXDCTL_WTHRESH 0x003F0000 e1000_hw.h TXDCTL Writeback Threshold
2880
E1000_TXDCTL_GRANE1000_TXDCTL_GRAN 0x01000000 e1000_hw.h TXDCTL Granularity
2881
E1000_TXDCTL_LWTHRESHE1000_TXDCTL_LWTHRESH 0xFE000000 e1000_hw.h TXDCTL Low Threshold
2882
E1000_TXDCTL_FULL_TX_DESC_WBE1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 e1000_hw.h GRAN=1, WTHRESH=1
2883
E1000_TXDCTL_COUNT_DESCE1000_TXDCTL_COUNT_DESC 0x00400000 e1000_hw.h Enable the counting of desc.
2884
E1000_TXDCTL_QUEUE_ENABLEE1000_TXDCTL_QUEUE_ENABLE 0x02000000 e1000_hw.h Enable specific Tx Queue
2885
E1000_TXCW_FDE1000_TXCW_FD 0x00000020 e1000_hw.h TXCW full duplex
2886
E1000_TXCW_HDE1000_TXCW_HD 0x00000040 e1000_hw.h TXCW half duplex
2887
E1000_TXCW_PAUSEE1000_TXCW_PAUSE 0x00000080 e1000_hw.h TXCW sym pause request
2888
E1000_TXCW_ASM_DIRE1000_TXCW_ASM_DIR 0x00000100 e1000_hw.h TXCW astm pause direction
2889
E1000_TXCW_PAUSE_MASKE1000_TXCW_PAUSE_MASK 0x00000180 e1000_hw.h TXCW pause request mask
2890
E1000_TXCW_RFE1000_TXCW_RF 0x00003000 e1000_hw.h TXCW remote fault
2891
E1000_TXCW_NPE1000_TXCW_NP 0x00008000 e1000_hw.h TXCW next page
2892
E1000_TXCW_CWE1000_TXCW_CW 0x0000ffff e1000_hw.h TxConfigWord mask
2893
E1000_TXCW_TXCE1000_TXCW_TXC 0x40000000 e1000_hw.h Transmit Config control
2894
E1000_TXCW_ANEE1000_TXCW_ANE 0x80000000 e1000_hw.h Auto-neg enable
2895
E1000_RXCW_CWE1000_RXCW_CW 0x0000ffff e1000_hw.h RxConfigWord mask
2896
E1000_RXCW_NCE1000_RXCW_NC 0x04000000 e1000_hw.h Receive config no carrier
2897
E1000_RXCW_IVE1000_RXCW_IV 0x08000000 e1000_hw.h Receive config invalid
2898
E1000_RXCW_CCE1000_RXCW_CC 0x10000000 e1000_hw.h Receive config change
2899
E1000_RXCW_CE1000_RXCW_C 0x20000000 e1000_hw.h Receive config
2900
E1000_RXCW_SYNCHE1000_RXCW_SYNCH 0x40000000 e1000_hw.h Receive config synch
2901
E1000_RXCW_ANCE1000_RXCW_ANC 0x80000000 e1000_hw.h Auto-neg complete
2902
E1000_TCTL_RSTE1000_TCTL_RST 0x00000001 e1000_hw.h software reset
2903
E1000_TCTL_ENE1000_TCTL_EN 0x00000002 e1000_hw.h enable tx
2904
E1000_TCTL_BCEE1000_TCTL_BCE 0x00000004 e1000_hw.h busy check enable
2905
E1000_TCTL_PSPE1000_TCTL_PSP 0x00000008 e1000_hw.h pad short packets
2906
E1000_TCTL_CTE1000_TCTL_CT 0x00000ff0 e1000_hw.h collision threshold
2907
E1000_TCTL_COLDE1000_TCTL_COLD 0x003ff000 e1000_hw.h collision distance
2908
E1000_TCTL_SWXOFFE1000_TCTL_SWXOFF 0x00400000 e1000_hw.h SW Xoff transmission
2909
E1000_TCTL_PBEE1000_TCTL_PBE 0x00800000 e1000_hw.h Packet Burst Enable
2910
E1000_TCTL_RTLCE1000_TCTL_RTLC 0x01000000 e1000_hw.h Re-transmit on late collision
2911
E1000_TCTL_NRTUE1000_TCTL_NRTU 0x02000000 e1000_hw.h No Re-transmit on underrun
2912
E1000_TCTL_MULRE1000_TCTL_MULR 0x10000000 e1000_hw.h Multiple request support
2913
E1000_TCTL_EXT_BST_MASKE1000_TCTL_EXT_BST_MASK 0x000003FF e1000_hw.h Backoff Slot Time
2914
E1000_TCTL_EXT_GCEX_MASKE1000_TCTL_EXT_GCEX_MASK 0x000FFC00 e1000_hw.h Gigabit Carry Extend Padding
2915
DEFAULT_80003ES2LAN_TCTL_EXT_GCDEFAULT_80003ES2LAN_TCTL_EXT_GC 0x00010000 e1000_hw.h  
2916
E1000_RXCSUM_PCSS_MASKE1000_RXCSUM_PCSS_MASK 0x000000FF e1000_hw.h Packet Checksum Start
2917
E1000_RXCSUM_IPOFLE1000_RXCSUM_IPOFL 0x00000100 e1000_hw.h IPv4 checksum offload
2918
E1000_RXCSUM_TUOFLE1000_RXCSUM_TUOFL 0x00000200 e1000_hw.h TCP / UDP checksum offload
2919
E1000_RXCSUM_IPV6OFLE1000_RXCSUM_IPV6OFL 0x00000400 e1000_hw.h IPv6 checksum offload
2920
E1000_RXCSUM_IPPCSEE1000_RXCSUM_IPPCSE 0x00001000 e1000_hw.h IP payload checksum enable
2921
E1000_RXCSUM_PCSDE1000_RXCSUM_PCSD 0x00002000 e1000_hw.h packet checksum disabled
2922
E1000_MRQC_ENABLE_MASKE1000_MRQC_ENABLE_MASK 0x00000003 e1000_hw.h  
2923
E1000_MRQC_ENABLE_VMDQE1000_MRQC_ENABLE_VMDQ 0x00000003 e1000_hw.h  
2924
E1000_MRQC_ENABLE_RSS_2QE1000_MRQC_ENABLE_RSS_2Q 0x00000001 e1000_hw.h  
2925
E1000_MRQC_ENABLE_RSS_INTE1000_MRQC_ENABLE_RSS_INT 0x00000004 e1000_hw.h  
2926
E1000_MRQC_RSS_FIELD_MASKE1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 e1000_hw.h  
2927
E1000_MRQC_RSS_FIELD_IPV4_TCPE1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 e1000_hw.h  
2928
E1000_MRQC_RSS_FIELD_IPV4E1000_MRQC_RSS_FIELD_IPV4 0x00020000 e1000_hw.h  
2929
E1000_MRQC_RSS_FIELD_IPV6_TCP_EE1000_MRQC_RSS_FIELD_IPV6_TCP_E 0x00040000 e1000_hw.h  
2930
E1000_MRQC_RSS_FIELD_IPV6_EXE1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 e1000_hw.h  
2931
E1000_MRQC_RSS_FIELD_IPV6E1000_MRQC_RSS_FIELD_IPV6 0x00100000 e1000_hw.h  
2932
E1000_MRQC_RSS_FIELD_IPV6_TCPE1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 e1000_hw.h  
2933
E1000_WUC_APMEE1000_WUC_APME 0x00000001 e1000_hw.h APM Enable
2934
E1000_WUC_PME_ENE1000_WUC_PME_EN 0x00000002 e1000_hw.h PME Enable
2935
E1000_WUC_PME_STATUSE1000_WUC_PME_STATUS 0x00000004 e1000_hw.h PME Status
2936
E1000_WUC_APMPMEE1000_WUC_APMPME 0x00000008 e1000_hw.h Assert PME on APM Wakeup
2937
E1000_WUC_SPME1000_WUC_SPM 0x80000000 e1000_hw.h Enable SPM
2938