構文
構文struct vxge_hw_mrpcim_reg
ファイル名
ファイル名構造体情報
構造体情報| No. | 名称 | 属性 | 説明 |
|---|---|---|---|
1 |
vxge_hw_mrpcim_reg | ||
| g3fbct_int_status | u64 | 0x00000 | |
| g3fbct_int_mask | 0x00008 | ||
| g3fbct_err_reg | u64 | 0x00010 | |
| g3fbct_err_mask | 0x00018 | ||
| g3fbct_err_alarm | u64 | 0x00020 | |
| unused00a00[0x00a00-0x00028] | u8 | ||
| wrdma_int_status | u64 | 0x00a00 | |
| wrdma_int_mask | 0x00a08 | ||
| rc_alarm_reg | u64 | 0x00a10 | |
| rc_alarm_mask | 0x00a18 | ||
| rc_alarm_alarm | u64 | 0x00a20 | |
| rxdrm_sm_err_reg | u64 | 0x00a28 | |
| rxdrm_sm_err_mask | 0x00a30 | ||
| rxdrm_sm_err_alarm | u64 | 0x00a38 | |
| rxdcm_sm_err_reg | u64 | 0x00a40 | |
| rxdcm_sm_err_mask | 0x00a48 | ||
| rxdcm_sm_err_alarm | u64 | 0x00a50 | |
| rxdwm_sm_err_reg | u64 | 0x00a58 | |
| rxdwm_sm_err_mask | 0x00a60 | ||
| rxdwm_sm_err_alarm | u64 | 0x00a68 | |
| rda_err_reg | u64 | 0x00a70 | |
| rda_err_mask | 0x00a78 | ||
| rda_err_alarm | u64 | 0x00a80 | |
| rda_ecc_db_reg | u64 | 0x00a88 | |
| rda_ecc_db_mask | 0x00a90 | ||
| rda_ecc_db_alarm | u64 | 0x00a98 | |
| rda_ecc_sg_reg | u64 | 0x00aa0 | |
| rda_ecc_sg_mask | 0x00aa8 | ||
| rda_ecc_sg_alarm | u64 | 0x00ab0 | |
| rqa_err_reg | u64 | 0x00ab8 | |
| rqa_err_mask | 0x00ac0 | ||
| rqa_err_alarm | u64 | 0x00ac8 | |
| frf_alarm_reg | u64 | 0x00ad0 | |
| frf_alarm_mask | 0x00ad8 | ||
| frf_alarm_alarm | u64 | 0x00ae0 | |
| rocrc_alarm_reg | u64 | 0x00ae8 | |
| rocrc_alarm_mask | 0x00af0 | ||
| rocrc_alarm_alarm | u64 | 0x00af8 | |
| wde0_alarm_reg | u64 | 0x00b00 | |
| wde0_alarm_mask | 0x00b08 | ||
| wde0_alarm_alarm | u64 | 0x00b10 | |
| wde1_alarm_reg | u64 | 0x00b18 | |
| wde1_alarm_mask | 0x00b20 | ||
| wde1_alarm_alarm | u64 | 0x00b28 | |
| wde2_alarm_reg | u64 | 0x00b30 | |
| wde2_alarm_mask | 0x00b38 | ||
| wde2_alarm_alarm | u64 | 0x00b40 | |
| wde3_alarm_reg | u64 | 0x00b48 | |
| wde3_alarm_mask | 0x00b50 | ||
| wde3_alarm_alarm | u64 | 0x00b58 | |
| unused00be8[0x00be8-0x00b60] | u8 | ||
| rx_w_round_robin_0 | u64 | 0x00be8 | |
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1(val) vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_ROUN | 0x00bf0 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9(val) vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_ROUN | 0x00bf8 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_R | 0x00c00 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_R | 0x00c08 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_R | 0x00c10 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_R | 0x00c18 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_R | 0x00c20 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_R | 0x00c28 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_R | 0x00c30 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_R | 0x00c38 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_ | 0x00c40 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_ | 0x00c48 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W_ | 0x00c50 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W | 0x00c58 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W | 0x00c60 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W | 0x00c68 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W | 0x00c70 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W | 0x00c78 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W | 0x00c80 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W | 0x00c88 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W | 0x00c90 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169(val) \ vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_W | 0x00c98 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1(val) vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_QUEUE_PRIO | 0x00ca0 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9(val) vxge_vBIT(val, 11, 5) #define VXGE_HW_RX_QUEUE_PRIO | 0x00ca8 | ||
| vxge_vBIT(val, 3, 5) u8 unused00cc8[0x00cc8-0x00cb0] | |||
| replication_queue_priority | u64 | 0x00cc8 | |
| vxge_vBIT(val, 59, 5) u64 rx_queue_select | 0x00cd0 | ||
| rqa_vpbp_ctrl | 0x00cd8 | ||
| rx_multi_cast_ctrl | 0x00ce0 | ||
| vxge_vBIT(val, 2, 30) #define VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_CNT(val) vxge_vBIT(val, 32, 32) u64 wde_prm_ctrl | 0x00ce8 | ||
| vxge_vBIT(val, 2, 10) #define VXGE_HW_WDE_PRM_CTRL_SPLIT_THRESHOLD(val) vxge_vBIT(val, 18, 14) #define VXGE_HW_WDE_PRM_CTRL_SPL | 0x00cf0 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_NOA_CTRL_NON_FRM_PRTY_QUOTA(val) vxge_vBIT(val, 11, 5) #define VXGE_HW_NOA_CTRL_IGNORE_KDF | 0x00cf8 | ||
| rcq_bypq_cfg | 0x00d00 | ||
| vxge_vBIT(val, 10, 22) #define VXGE_HW_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD(val) vxge_vBIT(val, 39, 9) #define VXGE_HW_RCQ_BYPQ_CFG_BY | |||
| doorbell_int_status | u64 | 0x00e00 | |
| doorbell_int_mask | 0x00e08 | ||
| kdfc_err_reg | u64 | 0x00e10 | |
| kdfc_err_mask | 0x00e18 | ||
| kdfc_err_reg_alarm | u64 | 0x00e20 | |
| unused00e40[0x00e40-0x00e28] | |||
| kdfc_vp_partition_0 | u64 | 0x00e40 | |
| vxge_vBIT(val, 5, 3) #define VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_0(val) vxge_vBIT(val, 17, 15) #define VXGE_HW_KDFC_VP_PARTITION | 0x00e48 | ||
| vxge_vBIT(val, 5, 3) #define VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_2(val) vxge_vBIT(val, 17, 15) #define VXGE_HW_KDFC_VP_PARTITION | 0x00e50 | ||
| vxge_vBIT(val, 5, 3) #define VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_4(val) vxge_vBIT(val, 17, 15) #define VXGE_HW_KDFC_VP_PARTITION | 0x00e58 | ||
| vxge_vBIT(val, 5, 3) #define VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_6(val) vxge_vBIT(val, 17, 15) #define VXGE_HW_KDFC_VP_PARTITION | 0x00e60 | ||
| vxge_vBIT(val, 17, 15) #define VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_9(val) vxge_vBIT(val, 49, 15) u64 kdfc_vp_partition_5 | 0x00e68 | ||
| vxge_vBIT(val, 17, 15) #define VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_11(val) vxge_vBIT(val, 49, 15) u64 kdfc_vp_partition_6 | 0x00e70 | ||
| vxge_vBIT(val, 17, 15) #define VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_13(val) vxge_vBIT(val, 49, 15) u64 kdfc_vp_partition_7 | 0x00e78 | ||
| vxge_vBIT(val, 17, 15) #define VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_15(val) vxge_vBIT(val, 49, 15) u64 kdfc_vp_partition_8 | 0x00e80 | ||
| vxge_vBIT(val, 17, 15) u64 kdfc_w_round_robin_0 | 0x00e88 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1(val) vxge_vBIT(val, 11, 5) #define VXGE_HW_KDFC_W_ROUND_ROBI | |||
| kdfc_w_round_robin_20 | u64 | 0x00f28 | |
| vxge_vBIT(val, 3, 5) #define VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_1(val) vxge_vBIT(val, 11, 5) #define VXGE_HW_KDFC_W_ROUND_ROB | |||
| kdfc_w_round_robin_40 | u64 | 0x00fc8 | |
| vxge_vBIT(val, 3, 5) #define VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_1(val) vxge_vBIT(val, 11, 5) #define VXGE_HW_KDFC_W_ROUND_ROB | |||
| kdfc_entry_type_sel_0 | u64 | 0x01068 | |
| vxge_vBIT(val, 6, 2) #define VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1(val) vxge_vBIT(val, 14, 2) #define VXGE_HW_KDFC_ENTRY_TYPE_ | 0x01070 | ||
| vxge_vBIT(val, 6, 2) u64 kdfc_fifo_0_ctrl | 0x01078 | ||
| vxge_vBIT(val, 3, 5) #define VXGE_HW_WEIGHTED_RR_SERVICE_STATES 176 #define VXGE_HW_WRR_FIFO_SERVICE_STATES 153 u8 unused11 | |||
| kdfc_fifo_17_ctrl | u64 | 0x01100 | |
| vxge_vBIT(val, 3, 5) u8 unused1600[0x01600-0x1108] | |||
| rxmac_int_status | u64 | 0x01600 | |
| rxmac_int_mask | 0x01608 | ||
| unused01618[0x01618-0x01610] | u8 | ||
| rxmac_gen_err_reg | u64 | 0x01618 | |
| rxmac_gen_err_mask | u64 | 0x01620 | |
| rxmac_gen_err_alarm | u64 | 0x01628 | |
| rxmac_ecc_err_reg | u64 | 0x01630 | |
| vxge_vBIT(val, 0, 4) #define VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR(val) \ vxge_vBIT(val, 4, 4) #define VXGE | 0x01638 | ||
| rxmac_ecc_err_alarm | u64 | 0x01640 | |
| rxmac_various_err_reg | u64 | 0x01648 | |
| rxmac_various_err_mask | 0x01650 | ||
| rxmac_various_err_alarm | u64 | 0x01658 | |
| rxmac_gen_cfg | u64 | 0x01660 | |
| rxmac_authorize_all_addr | 0x01668 | ||
| rxmac_authorize_all_vid | 0x01670 | ||
| unused016c0[0x016c0-0x01678] | |||
| rxmac_red_rate_repl_queue | u64 | 0x016c0 | |
| vxge_vBIT(val, 0, 4) #define VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1(val) vxge_vBIT(val, 4, 4) #define VXGE_HW_RXMAC_RED_R | |||
| rxmac_cfg0_port[3] | u64 | 0x016e0 | |
| vxge_vBIT(val, 50, 14) u8 unused01710[0x01710-0x016f8] | |||
| rxmac_cfg2_port[3] | u64 | 0x01710 | |
| rxmac_pause_cfg_port[3] | 0x01728 | ||
| vxge_vBIT(val, 9, 3) #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_DUAL_THR vxge_mBIT(15) #define VXGE_HW_RXMAC_PAUSE_CFG_PORT_HIGH_PTIM | |||
| rxmac_red_cfg0_port[3] | u64 | 0x01758 | |
| rxmac_red_cfg1_port[3] | 0x01770 | ||
| rxmac_red_cfg2_port[3] | 0x01788 | ||
| rxmac_link_util_port[3] | 0x017a0 | ||
| vxge_vBIT(val, 1, 7) #define VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG(val) vxge_vBIT(val, 8, 4) #define VXGE_HW_RXMAC_LINK_UT | |||
| rxmac_status_port[3] | u64 | 0x017d0 | |
| unused01800[0x01800-0x017e8] | |||
| rxmac_rx_pa_cfg0 | u64 | 0x01800 | |
| rxmac_rx_pa_cfg1 | 0x01808 | ||
| unused01828[0x01828-0x01810] | |||
| rts_mgr_cfg0 | u64 | 0x01828 | |
| vxge_vBIT(val, 24, 8) #define VXGE_HW_RTS_MGR_CFG0_ICMP_TRASH vxge_mBIT(35) #define VXGE_HW_RTS_MGR_CFG0_TCPSYN_TRASH vxge_mBIT | 0x01830 | ||
| rts_mgr_criteria_priority | 0x01838 | ||
| vxge_vBIT(val, 5, 3) #define VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN(val) vxge_vBIT(val, 9, 3) #define VXGE_HW_RTS_MGR_CR | 0x01840 | ||
| vxge_vBIT(val, 0, 17) u64 rts_mgr_da_slow_proto_cfg | 0x01848 | ||
| vxge_vBIT(val, 0, 17) u8 unused01890[0x01890-0x01850] | |||
| rts_mgr_cbasin_cfg | u64 | 0x01890 | |
| unused01968[0x01968-0x01898] | u8 | ||
| dbg_stat_rx_any_frms | u64 | 0x01968 | |
| vxge_vBIT(val, 0, 8) #define VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS(val) vxge_vBIT(val, 8, 8) #define VXGE_HW_DBG_STAT_ | |||
| rxmac_red_rate_vp[17] | u64 | 0x01a00 | |
| vxge_vBIT(val, 0, 4) #define VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR1(val) vxge_vBIT(val, 4, 4) #define VXGE_HW_RXMAC_RED_RATE_VP_C | |||
| xgmac_int_status | u64 | 0x01e00 | |
| xgmac_int_mask | 0x01e08 | ||
| xmac_gen_err_reg | u64 | 0x01e10 | |
| vxge_vBIT(val, 40, 2) #define VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR(val) \ vxge_vBIT(val, 42, 2) #define VXGE | 0x01e18 | ||
| xmac_gen_err_alarm | u64 | 0x01e20 | |
| xmac_link_err_port0_reg | u64 | 0x01e28 | |
| xmac_link_err_port0_mask | 0x01e30 | ||
| xmac_link_err_port0_alarm | u64 | 0x01e38 | |
| xmac_link_err_port1_reg | u64 | 0x01e40 | |
| xmac_link_err_port1_mask | u64 | 0x01e48 | |
| xmac_link_err_port1_alarm | u64 | 0x01e50 | |
| xgxs_gen_err_reg | u64 | 0x01e58 | |
| xgxs_gen_err_mask | 0x01e60 | ||
| xgxs_gen_err_alarm | u64 | 0x01e68 | |
| asic_ntwk_err_reg | u64 | 0x01e70 | |
| asic_ntwk_err_mask | 0x01e78 | ||
| asic_ntwk_err_alarm | u64 | 0x01e80 | |
| asic_gpio_err_reg | u64 | 0x01e88 | |
| asic_gpio_err_mask | 0x01e90 | ||
| asic_gpio_err_alarm | u64 | 0x01e98 | |
| xgmac_gen_status | u64 | 0x01ea0 | |
| xgmac_gen_fw_memo_status | 0x01ea8 | ||
| vxge_vBIT(val, 0, 17) u64 xgmac_gen_fw_memo_mask | 0x01eb0 | ||
| vxge_vBIT(val, 0, 64) u64 xgmac_gen_fw_vpath_to_vsport_status | 0x01eb8 | ||
| vxge_vBIT(val, 0, 17) u64 xgmac_main_cfg_port[2] | 0x01ec0 | ||
| unused01f40[0x01f40-0x01ed0] | |||
| xmac_gen_cfg | u64 | 0x01f40 | |
| vxge_vBIT(val, 2, 2) #define VXGE_HW_XMAC_GEN_CFG_TX_HEAD_DROP_WHEN_FAULT vxge_mBIT(7) #define VXGE_HW_XMAC_GEN_CFG_FAULT_BEHAV | 0x01f48 | ||
| vxge_vBIT(val, 6, 2) #define VXGE_HW_XMAC_TIMESTAMP_INTERVAL(val) vxge_vBIT(val, 12, 4) #define VXGE_HW_XMAC_TIMESTAMP_TIMER_RE | 0x01f50 | ||
| vxge_vBIT(val, 4, 4) #define VXGE_HW_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER(val) vxge_vBIT(val, 8, 4) #define VXGE_HW_XMAC_STATS_GE | 0x01f58 | ||
| vxge_vBIT(val, 5, 3) #define VXGE_HW_XMAC_STATS_SYS_CMD_STROBE vxge_mBIT(15) #define VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(val) vx | 0x01f60 | ||
| vxge_vBIT(val, 0, 64) u8 unused01f80[0x01f80-0x01f68] | |||
| asic_ntwk_ctrl | u64 | 0x01f80 | |
| asic_ntwk_cfg_show_port_info | 0x01f88 | ||
| asic_ntwk_cfg_port_num | 0x01f90 | ||
| xmac_cfg_port[3] | 0x01f98 | ||
| xmac_station_addr_port[2] | 0x01fb0 | ||
| vxge_vBIT(val, 0, 48) u8 unused02020[0x02020-0x01fc0] | |||
| lag_cfg | u64 | 0x02020 | |
| vxge_vBIT(val, 8, 8) u64 lag_active_passive_cfg | 0x02030 | ||
| vxge_vBIT(val, 32, 16) u8 unused02040[0x02040-0x02038] | |||
| lag_lacp_cfg | u64 | 0x02040 | |
| lag_timer_cfg_1 | 0x02048 | ||
| vxge_vBIT(val, 0, 16) #define VXGE_HW_LAG_TIMER_CFG_1_SLOW_PER(val) vxge_vBIT(val, 16, 16) #define VXGE_HW_LAG_TIMER_CFG_1_SHOR | 0x02050 | ||
| vxge_vBIT(val, 0, 16) #define VXGE_HW_LAG_TIMER_CFG_2_AGGR_WAIT(val) vxge_vBIT(val, 16, 16) #define VXGE_HW_LAG_TIMER_CFG_2_SHO | 0x02058 | ||
| vxge_vBIT(val, 0, 48) #define VXGE_HW_LAG_SYS_ID_USE_PORT_ADDR vxge_mBIT(51) #define VXGE_HW_LAG_SYS_ID_ADDR_SEL vxge_mBIT(55) | 0x02060 | ||
| vxge_vBIT(val, 0, 16) u8 unused02070[0x02070-0x02068] | |||
| lag_aggr_addr_cfg[2] | u64 | 0x02070 | |
| vxge_vBIT(val, 0, 48) #define VXGE_HW_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR vxge_mBIT(51) #define VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR_SEL | 0x02080 | ||
| vxge_vBIT(val, 0, 16) u64 lag_aggr_admin_key[2] | 0x02090 | ||
| vxge_vBIT(val, 0, 16) u64 lag_aggr_alt_admin_key | 0x020a0 | ||
| vxge_vBIT(val, 0, 16) #define VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR vxge_mBIT(19) u64 lag_aggr_oper_key[2] | 0x020a8 | ||
| vxge_vBIT(val, 0, 16) u64 lag_aggr_partner_sys_id[2] | 0x020b8 | ||
| vxge_vBIT(val, 0, 48) u64 lag_aggr_partner_info[2] | 0x020c8 | ||
| vxge_vBIT(val, 0, 16) #define VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY(val) \ vxge_vBIT(val, 16, 16) u64 lag_aggr_state[2] | 0x020d8 | ||
| unused020f0[0x020f0-0x020e8] | |||
| lag_port_cfg[2] | u64 | 0x020f0 | |
| lag_port_actor_admin_cfg[2] | 0x02100 | ||
| vxge_vBIT(val, 0, 16) #define VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI(val) vxge_vBIT(val, 16, 16) #define VXGE_HW_LAG_PORT_AC | 0x02110 | ||
| lag_port_partner_admin_sys_id[2] | 0x02120 | ||
| vxge_vBIT(val, 0, 48) u64 lag_port_partner_admin_cfg[2] | 0x02130 | ||
| vxge_vBIT(val, 0, 16) #define VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_KEY(val) vxge_vBIT(val, 16, 16) #define VXGE_HW_LAG_PORT_PARTN | 0x02140 | ||
| lag_port_to_aggr[2] | 0x02150 | ||
| vxge_vBIT(val, 0, 16) #define VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_VLD_ID vxge_mBIT(19) u64 lag_port_actor_oper_key[2] | 0x02160 | ||
| vxge_vBIT(val, 0, 16) u64 lag_port_actor_oper_state[2] | 0x02170 | ||
| lag_port_partner_oper_sys_id[2] | 0x02180 | ||
| vxge_vBIT(val, 0, 48) u64 lag_port_partner_oper_info[2] | 0x02190 | ||
| vxge_vBIT(val, 0, 16) #define VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY(val) \ vxge_vBIT(val, 16, 16) #define VXGE_HW_LAG_POR | 0x021a0 | ||
| lag_port_state_vars[2] | 0x021b0 | ||
| vxge_vBIT(val, 6, 2) #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_AGGR_NUM vxge_mBIT(11) #define VXGE_HW_LAG_PORT_STATE_VARS_LAGC_P | 0x021c0 | ||
| vxge_vBIT(val, 0, 8) #define VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_WHILE(val) \ vxge_vBIT(val, 8, 8) #define VXGE_HW_LAG_PO | |||
| rtdma_int_status | u64 | 0x02700 | |
| rtdma_int_mask | 0x02708 | ||
| pda_alarm_reg | u64 | 0x02710 | |
| pda_alarm_mask | 0x02718 | ||
| pda_alarm_alarm | u64 | 0x02720 | |
| pcc_error_reg | u64 | 0x02728 | |
| pcc_error_mask | 0x02730 | ||
| pcc_error_alarm | u64 | 0x02738 | |
| lso_error_reg | u64 | 0x02740 | |
| lso_error_mask | 0x02748 | ||
| lso_error_alarm | u64 | 0x02750 | |
| sm_error_reg | u64 | 0x02758 | |
| sm_error_mask | 0x02760 | ||
| sm_error_alarm | u64 | 0x02768 | |
| unused027a8[0x027a8-0x02770] | u8 | ||
| txd_ownership_ctrl | u64 | 0x027a8 | |
| pcc_cfg | 0x027b0 | ||
| pcc_control | 0x027b8 | ||
| vxge_vBIT(val, 6, 2) #define VXGE_HW_PCC_CONTROL_EARLY_ASSIGN_EN vxge_mBIT(15) #define VXGE_HW_PCC_CONTROL_UNBLOCK_DB_ERR vxge_ | 0x027c0 | ||
| vxge_vBIT(val, 4, 4) #define VXGE_HW_PDA_STATUS1_PDA_WRAP_1_CTR(val) vxge_vBIT(val, 12, 4) #define VXGE_HW_PDA_STATUS1_PDA_WRAP | 0x027c8 | ||
| vxge_vBIT(val, 12, 4) u8 unused02900[0x02900-0x027d0] | |||
| g3cmct_int_status | u64 | 0x02900 | |
| g3cmct_int_mask | 0x02908 | ||
| g3cmct_err_reg | u64 | 0x02910 | |
| g3cmct_err_mask | 0x02918 | ||
| g3cmct_err_alarm | u64 | 0x02920 | |
| unused03000[0x03000-0x02928] | u8 | ||
| mc_int_status | u64 | 0x03000 | |
| mc_int_mask | 0x03008 | ||
| mc_err_reg | u64 | 0x03010 | |
| mc_err_mask | 0x03018 | ||
| mc_err_alarm | u64 | 0x03020 | |
| grocrc_alarm_reg | u64 | 0x03028 | |
| grocrc_alarm_mask | 0x03030 | ||
| grocrc_alarm_alarm | u64 | 0x03038 | |
| unused03100[0x03100-0x03040] | u8 | ||
| rx_thresh_cfg_repl | u64 | 0x03100 | |
| vxge_vBIT(val, 0, 8) #define VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR(val) vxge_vBIT(val, 8, 8) #define VXGE_HW_RX_THRESH_CFG_ | |||
| fbmc_ecc_cfg | u64 | 0x033b8 | |
| vxge_vBIT(val, 3, 5) u8 unused03400[0x03400-0x033c0] | |||
| pcipif_int_status | u64 | 0x03400 | |
| pcipif_int_mask | 0x03408 | ||
| dbecc_err_reg | u64 | 0x03410 | |
| dbecc_err_mask | 0x03418 | ||
| dbecc_err_alarm | u64 | 0x03420 | |
| sbecc_err_reg | u64 | 0x03428 | |
| sbecc_err_mask | 0x03430 | ||
| sbecc_err_alarm | u64 | 0x03438 | |
| general_err_reg | u64 | 0x03440 | |
| general_err_mask | 0x03448 | ||
| general_err_alarm | u64 | 0x03450 | |
| srpcim_msg_reg | u64 | 0x03458 |
See Also
目次 | ファイル一覧 | 関数一覧 | ネームスペース一覧 | クラス一覧 | #define一覧 | マクロ一覧 | 外部変数一覧 | 構造体一覧 | 共用体一覧 | 列挙体一覧 | Const一覧 | 索引 | サイドメニュー