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hermonprm_mt25208_type0_st

構文構文

Little Endian

struct hermonprm_mt25208_type0_st

ファイル名ファイル名

MT25408_PRM.h

構造体情報構造体情報

No. 名称 属性説明
1
hermonprm_mt25208_type0_st  Little Endian
  vendor_id[0x00010] pseudo_bit_t Hardwired to 0x15B3
  device_id[0x00010] pseudo_bit_t 25208 (decimal) - InfiniHost-III compatible mode
  command[0x00010] pseudo_bit_t PCI Command Register
  status[0x00010] pseudo_bit_t PCI Status Register
  revision_id[0x00008] pseudo_bit_t  
  class_code_hca_class_code[0x00018] pseudo_bit_t  
  cache_line_size[0x00008] pseudo_bit_t Cache Line Size
  latency_timer[0x00008] pseudo_bit_t  
  header_type[0x00008] pseudo_bit_t hardwired to zero
  bist[0x00008] pseudo_bit_t  
  bar0_ctrl[0x00004] pseudo_bit_t hard-wired to 0100
  reserved0[0x00010] pseudo_bit_t  
  bar0_l[0x0000c] pseudo_bit_t Lower bits of BAR0 (Device Configuration Space)
  bar0_h[0x00020] pseudo_bit_t Upper 32 bits of BAR0 (Device Configuration Space)
  bar1_ctrl[0x00004] pseudo_bit_t Hardwired to 1100
  reserved1[0x00010] pseudo_bit_t  
  bar1_l[0x0000c] pseudo_bit_t Lower bits of BAR1 (User Access Region - UAR - space)
  bar1_h[0x00020] pseudo_bit_t upper 32 bits of BAR1 (User Access Region - UAR - space)
  bar2_ctrl[0x00004] pseudo_bit_t Hardwired to 1100
  reserved2[0x00010] pseudo_bit_t  
  bar2_l[0x0000c] pseudo_bit_t Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed.
  bar2_h[0x00020] pseudo_bit_t Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed.
  cardbus_cis_pointer[0x00020] pseudo_bit_t  
  subsystem_vendor_id[0x00010] pseudo_bit_t Specified by the device NVMEM configuration
  subsystem_id[0x00010] pseudo_bit_t Specified by the device NVMEM configuration
  expansion_rom_enable[0x00001] pseudo_bit_t Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration.
  reserved3[0x0000a] pseudo_bit_t  
  expansion_rom_base_address[0x00015] pseudo_bit_t Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration.
  capabilities_pointer[0x00008] pseudo_bit_t Specified by the device NVMEM configuration
  reserved4[0x00018] pseudo_bit_t  
  reserved5[0x00020] pseudo_bit_t  
  interrupt_line[0x00008] pseudo_bit_t  
  interrupt_pin[0x00008] pseudo_bit_t  
  min_gnt[0x00008] pseudo_bit_t  
  max_latency[0x00008] pseudo_bit_t  
  reserved6[0x00100] pseudo_bit_t  
  msi_cap_id[0x00008] pseudo_bit_t  
  msi_next_cap_ptr[0x00008] pseudo_bit_t  
  msi_en[0x00001] pseudo_bit_t  
  multiple_msg_cap[0x00003] pseudo_bit_t  
  multiple_msg_en[0x00003] pseudo_bit_t  
  cap_64_bit_addr[0x00001] pseudo_bit_t  
  reserved7[0x00008] pseudo_bit_t  
  msg_addr_l[0x00020] pseudo_bit_t  
  msg_addr_h[0x00020] pseudo_bit_t  
  msg_data[0x00010] pseudo_bit_t  
  reserved8[0x00010] pseudo_bit_t  
  reserved9[0x00080] pseudo_bit_t  
  pm_cap_id[0x00008] pseudo_bit_t Power management capability ID - 01h
  pm_next_cap_ptr[0x00008] pseudo_bit_t  
  pm_cap[0x00010] pseudo_bit_t [2:0] Version - 02h
  pm_status_control[0x00010] pseudo_bit_t [14:13] - Data scale - 0h
  pm_control_status_brdg_ext[0x00008] pseudo_bit_t  
  data[0x00008] pseudo_bit_t  
  reserved10[0x00040] pseudo_bit_t  
  vpd_cap_id[0x00008] pseudo_bit_t 03h
  vpd_next_cap_id[0x00008] pseudo_bit_t  
  vpd_address[0x0000f] pseudo_bit_t  
  f[0x00001] pseudo_bit_t  
  vpd_data[0x00020] pseudo_bit_t  
  reserved11[0x00040] pseudo_bit_t  
  pciex_cap_id[0x00008] pseudo_bit_t PCI-Express capability ID - 10h
  pciex_next_cap_ptr[0x00008] pseudo_bit_t  
  pciex_cap[0x00010] pseudo_bit_t [3:0] Capability version - 1h
  device_cap[0x00020] pseudo_bit_t [2:0] Max_Payload_Size supported - 2h
  device_control[0x00010] pseudo_bit_t  
  device_status[0x00010] pseudo_bit_t  
  link_cap[0x00020] pseudo_bit_t [3:0] Maximum Link Speed - 1h
  link_control[0x00010] pseudo_bit_t  
  link_status[0x00010] pseudo_bit_t [3:0] Link Speed - 1h
  reserved12[0x00260] pseudo_bit_t  
  advanced_error_reporting_cap_id[0x00010] pseudo_bit_t 0001h.
  capability_version[0x00004] pseudo_bit_t 1h
  next_capability_offset[0x0000c] pseudo_bit_t 0h
  uncorrectable_error_status_register[0x00020] pseudo_bit_t 0 Training Error Status
  uncorrectable_error_mask_register[0x00020] pseudo_bit_t 0 Training Error Mask
  uncorrectable_severity_mask_register[0x00020] pseudo_bit_t 0 Training Error Severity
  correctable_error_status_register[0x00020] pseudo_bit_t 0 Receiver Error Status
  correctable_error_mask_register[0x00020] pseudo_bit_t 0 Receiver Error Mask
  advance_error_capabilities_and_control_register[0x00020] pseudo_bit_t  
  header_log_register hermonprm_header_log_register_st  
  reserved13[0x006a0] pseudo_bit_t  

See Also

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